Triad Semiconductor designs and manufactures full-custom analog and mixed signal ASICs

We design full-custom analog and mixed signal ASICs to your specification

Our IC design team will partner with you to convert your design ideas into an optimized full-custom ASIC based on your specification. We utilize a rigorous ISO-certified design process that has been refined through the process of delivering hundreds of successful custom ICs to production.

Our patented methodology makes your custom ASIC reconfigurable with a single via mask layer change

Triad has invented, patented and refined via-reconfigurable ASIC technology. We make full-custom circuitry reconfigurable by overlaying these circuits with our patented via configurable routing fabric.

Triad’s Patented Via Reconfigurable Technology

Unique to Triad’s patented via reconfigurable approach, we overlay carefully chosen sections of the ASIC with specially designed routing fabric that is hand placed by a full-custom IC design expert. In the digital section of the device, where noise concerns are less, the fabric pattern will look very regular and uniform. In the analog portion of the IC, the fabric will look significantly more hand-crafted.

Figure 1 – Un-configured Routing Fabric
Figure 1 – Un-configured Routing Fabric
Figure 2 – Via-configured Fabric
Figure 2 – Via-configured Fabric

Via-Reconfigurable Full-Custom ASIC Benefits

The combination of full-custom circuitry with our patented routing fabric delivers powerful benefits. Both the interconnection and configuration of the analog and digital resources within your ASIC can be re-configured by changing a single via mask layer between the routing fabric layers.

Triad’s via reconfigurable intellectual property (IP) portfolio includes:

  • Full-custom analog and mixed-signal circuits
  • Via reconfigurable fabric associated with these circuits
  • Electronic design automation (EDA) software that knows how to place vias to re-configure the IP

Triad’s reconfigurable tile IP

We design and group together useful combinations of proven circuitry and via configurable fabric into a reuse-able IP resource that we refer to as a tile.

Triad’s tile IP portfolio numbers over 150 proven tiles useful for implementing a wide variety of circuits. An example tile would be an op-amp tile. Such a tile consists of: multiple op-amps accompanied by arrays of capacitors, resistors, transistors and switches and local logic. The tile is then carefully overlaid with routing fabric. This op-amp tile is useful for making a variety of circuits including: programmable gain stages, active RC filters, switched capacitor filters, sigma delta modulators, integrators, etc. All of these circuits can be re-configured onto this op-amp tile by a single via mask layer change.

Figure 3 – Example of a reuse-able Triad Op-Amp Tile
Figure 3 – Example of a reuse-able Triad Op-Amp Tile
Figure 4 – Arrangement of various configurable IP resources (tiles) inside an ASIC
Figure 4 – Arrangement of various configurable IP resources (tiles) inside an ASIC

Our via reconfigurable ASIC methodology delivers significant time-to-market and total-cost of-ownership advantages.

We utilize this portfolio of via reconfigurable tile IP (circuits, fabric and software) to rapidly assemble ASICs for your application.

Your ASIC will be an optimum mixture of existing Triad tile IP and new full-custom IP to satisfy the performance and cost targets of your program. Where possible we reuse proven tile IP to satisfy your requirements. This approach frees us to focus our design creativity and verification efforts on the most critical portions of your design that will have the greatest impact on differentiating your product in the market. This approach to ASIC design is fast, safe and highly profitable for our partners.

Triad’s Via Reconfigurable ASIC Benefits

  • Eight month Time-to-Market (TTM) advantage
  • 40% reduction in Total-Cost-of-Ownership (TCO)
  • Save over $2,000,000 in program TCO
  • Kick start your design with our proven IP portfolio
  • Mitigate Specification, Schedule and Performance Risks
  • Four week re-spins vs twelve weeks for traditional techniques
  • Quickly and cost effectively address emerging market Needs

Triad Time to Market Advantage

Time to Market Advantage
Table 1 – Triad’s Reconfigurable ASIC TTM Advantage
ASIC Development ActivityTriad Reconfigurable ASICs (weeks)Others – Traditional full-custom Only ASICs (weeks)
Design & Verification2024
Fabrication 11212
Rework 1411
Fabrication 24 (via mask only)12 (full mask)
Rework 2310
Fabrication 3412
Time-to-Market (start to production)47 weeks (11 months)81 weeks(19 months)

40% improvement in Time-to-Market with Triad’s approach.
How much is getting to market eight months earlier worth?

Table 2 – Triad’s Reconfigurable ASIC Single Project TCO Advantage
ASIC Development ActivityTriad Reconfigurable ASICs (cost)Others - Traditional full-custom Only ASICs (cost)
Design & Verification$400,000$400,000
Fabrication 1
Rework 1$100,000
Fabrication 2$100,000
Rework 2$20,000$50,000
Fabrication 3*$30,000$150,000*
Time-to-Market (start to production)$400K – $450K (33%-44% savings)$600K – $800K

* Note: Fabrication 3 costs are shown as $150K. This represents $100K for the tape out plus an additional $50K for fabrication expediting. As often happens on traditional designs. Expedite fees are used as a way to save 3-5 weeks in the fabrication process when the design is late to production. These expedite fees tend to be quite expensive compared to the amount of time they can actually save.

Table 3 – Triad’s Reconfigurable ASIC TCO Advantage Over 4 Designs
ASIC Development ActivityTriad Reconfigurable ASICs (cost)Others – Traditional full-custom Only ASICs (costs)
First ASIC Development$400,000$600K – $800K
Derivative ASIC #1$100,000$600K – $800K
Derivative ASIC #2$75,000$600K – $800K
Derivative ASIC #3$75,000$600K – $800K
Total-Cost-of-Ownership (TCO) for a 4 ASIC program$650,000 (70%-80% savings)$2.4M – $3.2M

With your Triad reconfigurable ASIC, optimized for your business, you can create four derivative IC products for less than the cost of two traditional full-custom ASIC developments.

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