In integrated circuit design, parasitic extraction is the calculation of parasitic effects in the circuit elements and wiring interconnect of the electronic circuit. The schematic for a circuit is represented by block elements such as resistors, capacitors, transistors and wires. When the design is actually laid out as polygons in a semiconductor device, parasitic elements are introduced. For example, two wires running close to each other represent some amount of capacitance. Wires and circuits also introduce parasitic resistance. These parasitic elements affect circuit performance. To account for these parasitic effects, the extracted parasitics can be back annotated to digital and analog simulations. In a digital simulation the parasitics mainly affect timing. In analog design PEX post layout simulation is required to determine parasitic effects related to sensitive analog circuit performance. PEX simulations are transistor level simulations and can be quite processor intensive. Typically, designers must exercise good design judgement and run PEX simulations on sensitive circuit areas but not on the entire chip owing to the inordinate amount of time required to run a full chip PEX simulation.

Triad Semiconductor performs parasitic extraction on all full custom and Agile ASIC designs. Triad’s Agile ASICs are full custom mixed signal circuits that are augmented with via reconfigurability. Agile circuits contain arrays of circuit elements such as resistors, capacitors, transistors, etc. These circuit collections are overlaid with patented routing fabric and circuits are configured and interconnected in an Agile ASIC by placing vias. Agile ASICs are single mask reconfigurable circuits. Agile ASICs offer some unique capabilities with regards to parasitics. A common post PEX simulation task is to move a track to reduce parasitic capacitance. In a traditional full custom design, it is difficult and time consuming to move such a track and prove that it improves performance. In the Agile ASIC design environment, a designer can go into the via place and route tool (ViaPath) and quickly move a track by selecting way points. Or the designer can move complete circuits by moving one resistor. ViaPath will detect the other circuits and tracks associated with that resistor and move them accordingly. These changes can be made in ViaPath in minutes. Such changes in full custom can take days or weeks.