Complimentary Metal Oxide Semiconductor is an integrated circuit fabrication technology. CMOS combines symmetrical and complimentary pairs of n-type and p-type field effect transistors (NFET and PFET transistors). CMOS circuits exhibit high noise immunity and low static power consumption. In general, CMOS circuits consume power when switching and use very little power when static. As CMOS process geometries have scaled down into deep sub micron (DSM), gate oxide thicknesses have been reduced to the point that static current leakage (power consumption) has become a greater concern. These CMOS leakage concerns started at 90nm, grew worse at 65nm and have required “beyond CMOS” process techniques to address leakage at geometries lower than 65nm. CMOS processes have been the backbone of the semiconductor industries for the past thirty years. Popular press about “Moore’s Law” semiconductor scaling have been primarily focused on the scaling of CMOS fabrication processes. CMOS has been a popular process for digital and memory circuit design due to the low static power consumption of the technology. Starting in the late 1990s through the early 2000s, foundries began adding analog and mixed signal capabilities to their digital CMOS processes. Today, CMOS process geometries from 0.35-micron down to 0.13-micron contain dense logic functions, 5-volt (low voltage analog capabilities), high voltage analog up to 80 volts and non-volatile memory such as EEPROM and Flash on the same process.

Triad Semiconductor has process and design know-how spanning process geometries from 1-micron to 65nm. Our IC design team has designed in CMOS, SiGe, GaAs and process technologies. For the majority of our analog and mixed signal customers we see mixed signal CMOS processes with geometries of 0.35-micron, 0.18-micron and 90nm as the ideal processes from a cost and performance perspective. Triad is a full service mixed signal ASIC company focused on the design and manufacture of custom ICs optimized for your application. We will work with you to specify a semiconductor process solution that is optimized for your application.