Digital synthesis involves first describing a logic function with a hardware description language (HDL) such as Verilog or VHDL. The digital synthesizer reads the HDL and realizes the circuit as a set of primitive combinatorial an memory elements (flip/flops and latches). The output of the synthesizer is a structural netlist of these components and their interconnections. Analog synthesis involves first describing an analog or mixed signal function in an analog or mixed signal HDL such as Verilog-A, VHDL-AMS or Verilog-AMS. The analog synthesizer reads the AMS HDL and realizes the circuit as a set of primitive analog and mixed signal elements (op-amps, resistors, capacitors, switches, etc.). Both analog and digital synthesis allow designers to think at a higher level of abstraction. Simulation at the HDL level can be orders of magnitude faster than structural netlist simulations (gate-level netlists or SPICE netlists).

Triad has been developing high-level mixed signal circuit models and analog synthesis for several years. Triad packages years of analog IC and IP design know-how into IP Generators. These IP Generators allow engineers with no IC design experience to create high-level system schematics without needing to know low-level chip design design. Triad’s IP Generators walk the user through parameterization forms to select various performance specifications for each block. Available IP Generators include functions such as: programmable gain stages, programmable instrumentation amplifiers, continuous time filters, switched capacitor integrators, sigma delta modulators, SAR ADC, etc. Circuits created with these high level models can be connected as IC system-level schematics for rapid simulation and analysis. Triad’s Analog Synthesis EDA software translates the high-level AMS HDL description of each circuit block into a realizable structural mixed signal circuit ready for place and route.