The 65nm process node became popular in 2006. The 65nm node is a in the Deep Submicron (DSM) category of process nodes. These nodes share common attributes as you go to smaller and smaller nodes: increasing logic density, smaller gate oxide thickness, lower operating voltage, faster switching speeds, and higher leakage currents. On nodes smaller that 90nm, wafers are typically larger in diameter resulting in a larger number of devices yielded per wafer and wafer boat. These attributes tend to make DSM nodes a good choice for ultra high volume digital-only applications but tend to make such nodes less ideal for mixed signal applications. The diminished voltage headroom makes analog design challenging at such nodes.

Triad provides ViaMask™ and DuoMask™ products for 65nm process nodes. ViaMask is a via configurable logic block that can be embedded into a System on a Chip (SoC) design. At 65nm all or a portion of the logic in the design can be implemented with the ViaMask block. This allows an SoC to support via-only changes to the logic functions. Some customers use this capability as a way to mitigate risk and provide a highly reliable and fast way to fix problems in an SoC that historically had been fixed with adhoc Spare Gate or Sewing Kit logic blocks. Additionally, ViaMask / DuoMask configurable blocks allow customer to quickly modify an SoC based on emerging market requirements or customer requests. Instead of making full maskset designs for 20 different mixed signal microprocessors, a single SoC with ViaMask configurable logic can be configured into 20 unique product offerings saving significant development time and fabrication costs.