The wearable technology market is a fast-paced market. As new products are introduced, the market responds resulting in rapidly evolving requirements. Companies looking to compete and win in the wearable market are faced with some formidable challenges.
Typically, fast time-to-market and lowest possible cost do not go together.
The customer chose Triad’s Hyper Agile ASIC approach to meet these two seemingly incompatible requirements of rapid development and lowest possible production cost.Triad created a new Agile ASIC from silicon-proven Agile Tile IP™. Agile Tiles are full-custom, high-performance circuits that are enhanced with Triad’s ViaOnly™ reconfigurability. These Agile Tiles contain medium-grained and fine-grained design resources such as op-amps, buffers, capacitors, resistors, switches, transistor
fingers and logic elements.
Complex analog, digital, and mixed-signal circuits can be configured and reconfigured onto an Agile ASIC by making ViaOnly™ single mask layer changes.
Since, the Agile Tiles were both silicon-proven and ViaOnly configurable, we were able to assemble the customer’s new ASIC and release the base layers of the ASIC to the foundry long before the circuit design was completed. Such an approach in a traditional full-custom-only methodology would be hazardous.
Upon receipt of first silicon, the customer discovered system issues that could not have been foreseen until the actual silicon was placed into the system. These issues required extensive circuit modifications. Schematic changes were made. The design was re-simulated. Next, the mixed-signal design was submitted to Triad’s ViaPath™ ViaOnly place and route software.
The required circuit changes would have required three to six weeks in a by-hand, full-custom approach. ViaPath was able to make ECO or incremental routing changes to place and route the revised design in hours.
Triad released a ViaOnly mask change to the foundry and new parts were fabricated, packaged and shipped to the customer in weeks.
Almost all mixed-signal ASICs need two to three passes to achieve production worthy silicon.
While digital ASICs often achieve first-time-right success, this simply is not the case with analog and mixed-signal custom ICs. Triad’s Agile Methodology reduces six-month respin cycles to 4 to 6 weeks.