The picture included with this post is a view of the GDSII of a full custom mixed signal ASIC. This ASIC is targeted at a high volume consumer electronics application. In this market, hitting cost targets is critical. A key driver for the cost of this custom IC is the silicon area. The design team was given a strict “not to exceed” die size budget.
Still, with all the emphasis on minimizing die area, note the black areas in the picture. Although black in the above picture, these areas are often referred to by designers as “white space” or completely unused silicon.
As the pictures show, even a high volume, cost sensitive full custom ASIC can end up having multiple rather large areas of unused or wasted silicon area.
8% to 10% of a Full Custom ASIC Often Goes Unused
In this example, 8% of the full custom area is going unused as shown in the pictures above and below. Now, when the design is actually shipped to the semiconductor foundry the IC die layout will not show these areas of “white space” or wasted silicon.
In a future post, we will show you how designers go about filling the wasted silicon area. It is rather strange the types of circuits and “non-circuits” that get stuffed in these white space sections throughout the chip.
In our next post, we will take a look at how can a high-volume, cost-sensitive full-custom design end up with some much wasted silicon area…It is a bit of a Forest for the Trees Problem…