# PID Controller Overview

The PID control architecture is well known for its ability to combine an immediate state, some past state(s), and the predicted future state(s) of a function f(I(t)) of the control loop input I(t) into a coordinated, present action.

While PID controller algorithms are routinely used for as mundane tasks as maintaining the desired level of a fluid in a storage tank, they are also applicable in more exciting (and time critical) tasks such as MAV multi – copter flight stabilization and vehicle engine control:

(1)

The immediate (P) control action is generated at a rate equivalent to the input to output delay (or propagation or sample) time of the PID controller loop as it repetitively executes. The history (I) action is a finite, scaled accumulation of past immediate states (beyond which recollection of past behavior is no longer deemed significant), and the anticipatory (D) action is a rate projection into the near future (again requiring the finite retention past state(s) to compare with the present state for trajectory calculation).

The response magnitudes and time scales of the PID controller algorithm are of course set by the variables Kp, Ki, and Kd in (1). Overall PID operation is first modeled in the Laplace (or s domain) using control system blocks:

Two ancillary models are provided to help demonstrate PID action. A changing process reference is modeled as a zero average triangle wave of a 0.2s period (a 0.1s ramp is a time constant or relaxation time in the physical world that we as humans commonly can perceive) and a load (representing an actuator impedance, electrical to thermal transducer or similar end effector) simulates the mechanism by which the PID signal affects to the outside world:

The actual PID contains the requisite P, I, and D portions along with integrator anti-windup and derivative filtering:

The PID proportional gain Kp = K is set at 1.0 for simulation:

The integral portion incorporates an anti-windup voltage controlled switch. In keeping with general VLSI design rules, voltage scaling is done by the ratio of resistances R3/(R2+R3), rather than absolute resistance magnitudes. With R2=R3, the overall gain of the integrator is Ki=k*0.5=2*0.5=1.0:

Derivative action has a tendency to cause large, unwanted control anticipations in many control loops if Kd is set too large. Therefore, Kd is set at a value Kd=0.1<<Kp, Kd<<Ki for simulation. The derivative filter (used to eliminate further noise from the derivative response) pole is set at 100Hz to provide a balance between first order LPF smoothing and rise (or response time) of the derivative portion of control, as well as to numerically mesh with multiple integrator sample intervals FSMP (set at 10000Hz in the integrator block above):

Because the PID controller integrator is implemented with ‘pure’ Laplacian integration k/s, the mathematical effect of any input, however small, is always accumulated. Because of this perpetual accumulation, the DC (essentially unchanging input of any magnitude) gain of k/s is effectively infinite, meaning that the integrator output can grow to unbounded size as time elapses, even with an infinitesimal (seemingly insignificant) input (ultimately the integrator will indeed be bounded by VLSI chip rail voltage or digital variable rollover, but dynamical response will be very unfavorable in these cases).

From a reaction time standpoint, unbounded integrator growth is very undesirable for proper control. For example, if a very small integrator input exists for a long time, the integrator state will grow very large and may eventually dominate the overall PID output.

While this diligent accumulative behavior may be mathematically correct (and is the also ‘proper’ behavior to completely eliminate steady state errors), when a significant input change does indeed occur after a lengthy time containing a very small input, the integrator is now ill prepared to respond and may take an inordinately long amount of time to eliminate (integrate away) the long duration, small amplitude. In many cases, this unpreparedness results in a lag in P+I+D output where P and D action are nullified by the I action, in turn control loop oscillations or even instability.

To overcome integral windup behavior, the integrator is typically saturated (stopped) at a value that will allow both an authoritative integral contribution during dynamic conditions and prevent the I portion of the P+I+D from growing too large over time when steady state error is very small (but still present).

One common way of achieving this is stopping the integrator when the PID output is at a predefined maximum, a maximum which can be caused by any individual P, I, or D response alone or in the sum of P+I+D in any proportions of P or I or D. The integrator is controlled using the absolute value of the limited PID output as a voltage input to a threshold SPST switch. The switch connects the integrator input to ground when PID output is at a maximum (25V) with a volt of hysteresis to prevent any limit cycling:

PID controller operation displays the classic calculus transformations for a triangle input signal using f(t) = reference(t)–feedback(t) (the so called regulation problem where reference(t)=constant=0.0). The (yellow trace) proportional response introduces a scalar transformation only, the integrator (blue trace) changes the linear triangle input into a parabolic and is disconnected when PID output is clipped, and the derivative (orange trace) transforms the linear triangle input into a square (constant) wave that is low pass filtered (purple trace) to eliminate noise excursions:

Fig. 10 PID traces for 1 second of simulation; input f(t) (green trace), P (yellow trace), I (blue trace), D (orange trace), D filtered (purple trace), and PID and limited PID output (cyan and brown traces respectively, bottom)

Note that the use of the control system blocks introduces only a minor spike in the raw derivative, which is then filtered by the derivative LPF:

## PID Controller OpAmp Realization in ViaDesigner

A PID implementation using simple op amps has several interesting advantages and disadvantages. Using the same triangle wave feedback and resistive load, the overall PID schematic is:

The difference amplifier needed to generate f(t) = reference(t)–feedback(t) is slightly more complex than the simple difference used in the control system block PID implementation. For reasons outlined below, the output of the summing junction is non inverting, buffered, and RSJ1=RSJ2=RSJ3=RSJ4:

Again using resistance ratios for VLSI implementations, to provide an ‘infinitely variable’ proportional gain P that can also be less than unity (a non inverting op amp scaling circuit would require additional resistances for gains less than unity), to lessen op amp count, and to take advantage of common inverting integrator and differentiator circuits while minimizing the need for cascaded inverting of P, I, and D signals for summing P+I+D, an inverting P circuit is selected:

The inverting op amp integrator has the distinct advantage of very simple anti wind up implementation. Resistor RI2=RI1 and RI1*CI1=1.0 implements a ‘lossy integrator’ with a maximum DC gain of 1.0. Additionally, any silicon op amp implementation would also saturate at the op amp rails supplying the chip, limiting the individual voltage magnitude of P, I and D (as well as their sum):

Due to the need to keep the sign of P, I and D identical (and negative), the common inverting differentiator requires non inverting buffers to limit the loading effects of Kd and the non inverting LPF for the derivative filter. With Kd=RD2/(RD1+RD2)=0.1, RD3* CD1=1.0, and the pole of the RC low pass filter RD4*CD2~=0.005 to damp the overshoot of the derivative square wave output, the D op amp section schematic is:

Finally, because each of P, I, and D are inverting, a simple inverting summer can be used to achieve –(-P-I-D)=P+I+D. Note that this inverting summer will also limit overall PID output at the +/- supply rails of any silicon realization in an actual IC:

## PID Controller Simulation

PID simulation behavior is very similar to that of the control system block simulation above, save for the step change ringing of the raw differentiator signal. Note that each of P, I, and D are (as expected) inverted in phase as compared to their counterparts in the control system block implementation of the PID above:

Fig. 18 OP amp PID simulation response, 1 second; input f(t) (green trace), P (yellow trace), I (blue trace), D (orange trace), filtered D (purple trace) and PID output (cyan trace)

Of note is that the op amp PID circuit can approximate the DC operation of the ideal, control system block PID circuit by simply by cascading buffer isolated op amp stages while noting preventing any unwanted signal inversions. This approach can be suboptimal, however, in terms of frequency response (as in the raw derivative and LPF of the above figure), and may result in internal circuit voltage excursions that will attempt to exceed (and be clipped at) the op amp rails, and thus require additional square wave harmonics to be attenuated via the derivative LPF.

As such, a more detailed frequency domain analysis of the op amp PID implementation over the range of expected input frequencies can yield better approximations to the ideal, control system block implementation, while still providing simplified integrator windup and intrinsic output voltage limiting capabilities:

Fig. 19 PID internal D signal amplitude ringing behavior; one period (top), zoomed in (bottom)

More information on Triad Semiconductor’s ViaDesigner Mixed Signal ASIC design environment.

If you have PID controller design requirements and would like to talk with a Triad ASIC application engineer (contact us).