Power consumption and performance are a delicate balance. For many applications, especially in the case of low power sensors, bandwidth requirements are typically well defined by the phenomena being measured.

For example the American Heart Association’s recommendation for the minimum bandwidth of a pediatric ECG waveform is 250Hz or 500 sps. A key requirement such as this one could help to derive sub-component requirements such as opamp bandwidth as well provide key information on how to configure a Sigma-Delta ADC modulator bandwidth, clock frequency and sample rate. See How to design a 16-bit Sigma Delta Analog to Digital Converter for more information.

Bandwidth vs Power

formula_unity-gain-bandwidthLet’s take a closer look at Bandwidth and Power tradeoffs. Specifically we will continue to analyze operational amplifiers however rules for opamps also apply to other ASIC elements as well. An opamp’s unity gain bandwidth (UGBW) is dependent on many aspects of its design, however one high-level tradeoff is the relationship between bias current and UGBW. This relationship is derived from the the formula at right. In this formula Aol is the open loop gain and fc is the dominant pole frequency. Assuming the pole frequency, diff pair topology and transistor sizing remains constant, Aol may be adjusted by scaling the bias current. This relationship is apparent in the chart below that lists a subset of Triad’s opamp designs from our IP portfolio. We are continuously building this portfolio with IP targeted at different applications and customer requirements.

unity-gain-bandwidth_plot

A chart showing a subset of Triad’s opamp designs from our IP portfolio.

Going back to the Low Power ECG example, perhaps a gain of 200 V/V (~46dB) is needed for the second stage of the ECG front end measuring the 250 Hz signal. The theoretical minimum unity gain bandwidth would be 250Hz * 200 = 50 kHz. In reality some margin may be desirable but if we continue with this low bandwidth assumption, the opamp bias current requirements could be in the range of 1-2 uA.

Low Power ASIC Design Series

This article is part of a five-part series on Low Power ASIC Design:

1) ASIC Integration Power Savings 2) Balancing Power and Performance3) Dynamic Power Control4) The Virtue of Power and Batteries5) Case Study: Wearable Air Quality Sensor