A new alternative to full-custom analog/mixed signal ASICs will be introduced. This new approach applies many of the concepts of deep-submicron digital structured arrays to larger geometry analog processes. Consequently a place-and-route tool (normally only for the digital domain) can be used to configure an analog ASIC while maintaining performance comparable to classical full-custom analog design. Specifically, this concept uses a single via layer to configure an entire semi-custom analog integrated circuit. These new devices are called via-configurable analog arrays (VCAAs.)
Jim Kemerling is the chief technical officer of Triad Semiconductor. At Triad, he is responsible for VCA technology development and implementation. His background includes over 25 years of experience with mixed-signal IC design and system-level development. Jim holds four patents and has published numerous papers. He received his Bachelor of Science in electrical engineering from South Dakota State University and his master’s in electronic engineering from the University of Nevada.
The EDA industry has focused primarily on the digital domain. And for good reason, this is where the volume has been. However, as we hear frequently, the world is analog and the need for analog ASICs will never go away. Since the beginning of the integrated circuit era, attempts have been made at automating the analog design and fabrication process. Most of these attempts have failed or only realized limited success due largely to the boundaries of digital EDA technology. Field-programmable analog arrays (FPAAs) have shown some promise. In particular, the floating gate technique does offer some hope, but is not gaining mainstream acceptance yet. Even if it does, its primary purpose will be in prototyping—analogous to the ubiquitous field-programmable gate array (FPGA) for digital circuits .
By definition, field-programmable devices cannot be identical to mask-programmable or full-custom devices. In other words, field programmability comes with significant overhead, making volume production impractical where size, weight and power are concerns. In addition to field-programmable approaches, there have been attempts at mask-programmable analog arrays. Typically in this case a device is configured for a specific application in the final metal layers. To date, this layout process has been a manual exercise which has proven to be very time-consuming and error-prone. Via-Configurable Analog Arrays (VCAAs) are an alternative that will not completely take the place of FPAAs or full-custom ASICs, but are a superior for many applications.
VCAAs, like digital-structured ASICs, have their origin in digital gate arrays. Gate arrays were first used in production in the late 1970s. The advantage of structured arrays or gate arrays comes from requiring fewer masks than a full-custom chip for configuration. A VCAA is a structured analog array requiring only a single via layer for customization .
Current semiconductor technologies generally have more than four metal layers. A via layer in the midst of these metal layers is ideal for configuration, allowing access to the metal layers above and below for routing without blocking signal tracks. Consequently, in a VCAA all the routing tracks are pre-defined (manually) forming a via-configurable routing fabric. This is essential for semi-custom analog since EDA companies have not created an effective analog place and route tool. In a via-configurable array a place and route tool is used, but only to place vias in the locations dictated by the routing fabric.
The VCAA concept can be used across an entire chip or in specific sections. For instance, it may be most effective to do a full-custom layout on sections of the chip that are well understood and not likely to change, but there may be other sections that need to change to support different customer requirements. Any section of a chip that is likely to change over time is an ideal candidate for via configurability.
VCAA technology can be applied to almost any analog circuit from a low speed, high resolution sensor interface to RF circuits. Signal conditioning and data conversion are requirements in almost any modern system and are straight forward to implement in a VCAA without manual layout while yielding performance comparable to full-custom designs. Furthermore, the via-configurable approach allows for the staging of wafers during fabrication at the configurable via layer resulting rapid turnaround time. Typically wafers staged at the via layer can be processed in less than a week compared to several weeks for all layer fabrication.
Via-Configurable Technology  
VCAAs are similar to structured ASICs and gate arrays. The difference between gate arrays and structured ASICs is not obvious, but the general consensus says structured ASICs tend to include predefined or configurable memories and/or analog blocks not normally found in gate arrays. A VCAA can be thought of as an analog structured array where only a via layer is used for configure it for a specific application.
Figure 1 is a simplified illustration showing the process of configuring a via-configurable fabric. Figure 1(a) shows the fabric with no vias, notice the fabric is made up of quadrants with each quadrant having routing tracks that are perpendicular to the routing tracks on the same metal layer in the adjacent quadrant. This minimizes the use of available routing tracks. Figure 1(b) shows the fabric with vias placed and the resulting routing. Unused tracks in the fabric can be used for shielding or alternative routing. Ultimately the only layer used to configure the entire VCAA is a single “configurable via layer” (CVL) between the two metal layers of the fabric as shown in Figure 1(c).
(a) (b) (c)
Figure 1: (a) Via-configurable routing fabric with no vias, (b) fabric with vias inserted, and (c) the via layer.
The via-configurable concept can be used across an entire chip or just in certain sections. For instance, it may be most effective to do a full custom layout on sections of the chip that are well understood and not likely to change, but there may be other sections that need to change to support different customer requirements. Any section of a chip that is likely to change over time is an ideal candidate for via-configurability.
VCAA Design Flow
The VCAA design flow, shown in Figure 2, is pretty standard on the front end. Namely schematic capture and simulation are done like always using a VCAA library. However, notice the VCAA design flow is absent of layout (polygon editing) and layout verification (DRC). This is due to the fact that the VCAA base platform (all the layers other than the configurable via layer) has already been completely verified prior to production release. Hence, the VCAA designer is able to focus on design capture and simulation.
Figure 2: VCAA design flow.
Analog IC Technology
Analog integrated circuits are primarily composed of transistors, resistors and capacitors. Resistors and capacitors generally vary in value significantly (10% – 20%) due to process variation and temperature, but can be effectively applied in circuits where their ratio takes precedence over their absolute value. In silicon, capacitors typically range in value from 0.1 pf to 10 pf and resistors range in value from 100 ohms to 1 Mohms. The ubiquitous transistor is used in analog circuits for switches and amplifiers.
The operational amplifier (opamp) is the most common cell in analog circuits. Analog standard product manufacturers produce a wide variety of opamps to suit many different application requirements. Early opamps were bipolar, but in the past 20 years CMOS opamps have become much more popular. Although bipolar opamps still have superiority in some parameters such as input referred noise and drive capability, CMOS opamps are able to meet the requirements of many applications. Most notably, CMOS opamps have very high input impedance (@ 1012 ohms) and generally consume less quiescent power. Some of the most common parameters referred to when selecting a CMOS opamp for a specific application are listed in Table 1.
|Gain bandwidth product||
0.1 – 1000
0.1 – 100
|Open loop output impedance||
1 – 10000
|DC open loop gain||
40 – 100
|Quiescent current consumption||
0.05 – 10
|Input referred offset voltage||
10 – 1000
|Input referred noise voltage||
0.1 – 10
Table 1: Some common CMOS opamp parameters.
The range in parameter values shown Table 1 is a direct result of the trade-offs confronting the opamp designer. In other words, it is impossible to create one opamp for all applications. For instance, for an opamp where GBW and SR are maximized, usually IDD will be high.
Figure 3 shows a simplified schematic of a two stage CMOS opamp. The input stage is formed by M1 – M5 and the output stage by M6 – M7. The bias current IB is mirrored to the input stage by the ratio of M8 to M3 and to the output stage by the ratio of M8 to M6. The amplifier is compensated by CC.
Figure 3: Two stage CMOS opamp.
It is not the intent of this paper to give a tutorial on opamp design, but rather to point out how allowing a few aspects of a given opamp to vary can affect some performance parameters. For instance, the GBW for the opamp of Figure 3 is given by
Where gm1 = gm2 is the transconductance of the input pair.
ID = drain current
W = transistor width
L = transistor length
Hence, the GBW for the opamp of Figure 3 is proportional to the square root of the drain current for the input pair which is set by IB. In other words the GBW can be increased by increasing IB. However, increasing IB also changes the transconductance of output transistors which will change the locations of the amplifier poles and zeros which may require a change in CC to maintain stability. The reader is referred to  for more detailed information on opamp design.
Analog Tile Concept
As mentioned earlier, analog circuits are composed of transistors, resistors and capacitors. In a VCAA these devices are arranged in a configuration known as a tile. The complete VCAA is composed of several analog tiles depending on the targeted applications. An example of an analog tile in a VCAA is shown below in Figure 4.
Figure 4: Analog tiles in a VCAA.
Notice the analog tile consists of an array of analog switches, an array of capacitors, an array of resistors, multiple amplifiers and some digital logic. The amplifiers in this tile example are operational transconductance amplifiers (OTA) as opposed to opamps. OTAs are essentially unbuffered opamps and work well for applications where only capacitive loads are encountered as is typical in an analog integrated circuit. In the case where it is necessary to drive a resistive load, an output stage (O/S) is provided which can be connected to the output of the OTA forming an opamp.
An example of a circuit implemented with an analog tile like the one shown in Figure 4 would be an active RC filter. Although it is difficult to maintain a constant cutoff frequency due to process variation and temperature shift, these types of filters have been successfully used for anti-aliasing filters preceding an ADC or switched capacitor circuit. Since process variation and temperature can cause resistors and capacitors to vary in value by as much as 20% it is important to make sure the cutoff frequency of the filter is more than a factor of two below the ADC sampling frequency.
Figure 5: (a) Active RC lowpass filter (b) implemented using analog tiles.
Fully Differential Circuits
On-chip analog signal processing is often accomplished with fully differential circuits due to their increased immunity to common mode noise and effective increase in dynamic range. Figure 6 shows an example of a fully differential analog tile. Notice the analog switches, capacitors, resistors are shown above and below the fully differential opamps. This represents the physical layout on-chip and is necessary for most fully differential circuits.
Figure 6: Fully differential analog tile in a VCAA.
Switched Capacitor Circuits 
Switched capacitor (SC) circuits are straight forward to implement in VCAA analog tiles. In SC circuits, resistors are replaced by switched capacitors. Although the value of a capacitor is subject to process variation and temperature shift, the ratio of one capacitor to another will track very well. As long as the capacitors are in the same array within an analog tile their ratios can maintain a tolerance of approximately 0.1 %. Consequently, gain and filter cutoff frequencies are set by the ratio of capacitors, not the absolute value.
Figure 7 shows an RC first order lowpass filter and its equivalent SC circuit.
Figure 7: (a) First order RC low pass filter and (b) its equivalent first order SC circuit.
The -3 dB cutoff frequency for the RC circuit is:
If TS is the period of the switch clock and then the -3 dB cutoff frequency for the SC circuit is:
In other words, SC networks will approximate the behavior of continuous-time RC circuits as long as the clock frequency is much higher than the signal frequency. SC networks are discrete-time, continuous-amplitude systems meaning they are governed by the rules of sampling theory.
In the network of Figure 7(b) the clocks (f1 and f2) must be non-overlapping (tNO). This insures proper charge transfer. In addition, the on-time for a switch must be long enough to guarantee complete charge transfer. Charge transfer is limited by the RC time constant formed by the switch on resistance and the capacitor being charged. This can be a limiting factor in switch clock speed, but in most cases other factors such as amplifier bandwidth are more dominant.
An issue with the SC network of Figure 7(b) is the capacitor’s values will be affected by parallel parasitic capacitance. If the value of the parasitic capacitance for C and CR do not match, there will be error in the cutoff frequency. Consequently, most SC circuits are implemented with parasitic insensitive structures, see Figure 8. As the name implies, these structures minimize or eliminate the effect of parasitic capacitance.
Figure 8: (a) Parasitic insensitive switched capacitor and (b) a parasitic insensitive negative resistance switched capacitor.
Like the switched capacitor in Figure 7(b), the switched capacitor resistance for the network of Figure 8(a) is
Figure 8(b) shows by swapping the clock phasing for the switches on the right side of the capacitor the effective resistance is negative.
This is an important aspect of SC circuits and helps in reducing network complexity.
The most common application of SC circuits is filtering. A straight forward method to develop SC filters is to model them after a continuous-time active circuit. Figure 9(a) shows the schematic for the popular Tow-Thomas biquad. This two integrator topology is capable of realizing 2nd order bandpass and lowpass filters. In Figure 9(b) the switched capacitor version is shown. Notice the stage with H(s) = -1 from the continuous time version is implemented in the SC version with a negative resistance. Finally in Figure 9(c) is the SC version that minimizes the use of switches by sharing. This is one of many SC biquad topologies. Some are optimized for low-Q applications while others are optimized for higher speed applications.
Figure 9: Transformation from (a) a continuous-time Tow-Thomas biquad to a (b) switched capacitor version and finally (c) a version where switches are shared.
SC filter implemented in a VCAA
Table 2 lists the requirements for a SC filter with a 4th order Butterworth transfer characteristic.
Table 2: Filter specifications.
A popular topology for the above filter uses two cascaded biquads (2nd order sections) as shown in Figure 10. The transfer function can be derived using a standard Butterworth s-domain transfer function and then converting it to a z-domain equivalent using the bilinear transform. The capacitor values can be calculated directly from the
z-domain transfer function . Alternatively, the continuous-time prototype can be designed and converted to an SC version.
Figure 10: Filter topology.
In analog IC design it is standard practice to use fully differential networks to implement high performance SC circuits. Particularly if the SC filter is the front end to an ADC with more than 10 bits of resolution. The biggest drawback of fully differential SC circuits is the number of capacitors and switches is doubled. Figure 11 shows a fully differential biquad topology suitable for implementing the SC filtered specified above. Note each SC biquad is an optimal fit for the fully differential analog tile.
Figure 11: Analog tile used to implement a switched capacitor 2nd order filter section.
As mentioned earlier, time constants for SC filters are set by capacitor ratios. Hence, the actual value of the individual capacitors is not important. The number of unit capacitors used for each capacitor in each 2nd order section, are listed in the tables below.
Table 3: Unit capacitors required for H1(z).
Table 4: Unit capacitors required for H2(z).
Note the capacitors listed in Table 3 and Table 4 are not integer multiples of the unit capacitor. C14 it is made up of 81 units plus a remainder of 1.3. The total number of units used in H1(z) is 174 plus a 1.3 remainder. H2(z) uses a total of 122 units + remainders of 1.1, 1.8 and 1.8. The total number of units plus remainders fits well within the available resources of two fully differential analog tiles.
Remember switched capacitor filters require two-phase non-overlapping clocks. Hence, the analog tile contains some logic, which can be used to generate multiple phases locally. This keeps the number of clock signals that must be routed through the VCAA to a minimum.
The reader is referred to  and  for additional information on SC circuits.
Sigma Delta Modulation ADC in a VCAA  
Sigma Delta Modulation ADCs are based on the concept of oversampling where the signal to be converted is sampled at a much higher frequency than the Nyquist frequency. Effectively this technique uses greater temporal accuracy to attain the desired amplitude resolution. The continuous-time input signal is oversampled and quantized into a one bit digital signal by the sigma delta modulator (SDM). The over sampling ratio (OSR) is the ratio of the SDM sampling frequency fS to the input signal frequency fIN.
Figure 12: Sigma Delta Modulation ADC block diagram.
The output of the SDM is accumulated and down-sampled by the decimation filter. The decimation factor N is the ratio of the SDM sampling frequency fS to the decimation filter output frequency fSO (Nyquist rate.)
Decimation filters essentially compute the average of the over sampled one bit signal from the SDM. The simplest decimation filter is an accumulator which can be implemented with an up/down counter where the output of the counter is sampled at the desired output sample frequency fSO. More complex structures, consisting of cascaded integrators and differentiators (commonly referred to as sinc filters) will yield better performance for a given decimation factor or allow a lower decimation factor.
A 1st order SDM block diagram is shown below in Figure 13.
Figure 13: 1st order Sigma Delta Modulator.
The achievable signal-to-noise for a 1st order SDM is given by EQ 7.
By rearranging EQ7 the OSR can be found for a required SNR.
For instance, if the desired SNR = 84 dB (14 bits) the required OSR for a 1st order SDM would be 516. If the input signal frequency is limited to 100 Hz (typical of low bandwidth sensors) the required SDM sampling frequency fS would be 51.6 kHz.
Implementing a 1st order SDM is straight forward with the components available in a single VCAA fully differential tile. A schematic is shown in Figure 14. The reference voltages VREF+ and VREF- can be tied to the positive and negative supply rails or other reference voltages can be realized using the resistors available in the tile. The gain of the integrator is set by the ratio of C1 and C2.
The value of G must be less than unity to avoid stability issues and keep the integrator from saturating.
Figure 14: 1st order SDM in a VCAA.
The 1st order SDM is suitable for low bandwidth applications, but for higher bandwidth applications the sample rate quickly becomes too high for practical implementation. In this case, higher order modulators and more complex decimation filters are required. The reader is referred to  for more detailed information.
A New Way to Develop Analog ASICs 
The cost of full custom ASIC mask tooling, and the time required for fabrication, make it virtually impossible to prototype a design in silicon. Designers are forced to rely on simulation and breadboard approximations which rarely mimic actual silicon behavior. When the chip finally comes back from the fab all too often some aspect the design is wrong and a 2nd fabrication cycle is required.
Since VCAAs only require a single layer for fabrication, prototyping in silicon is practical. In fact, multiple versions of a design can be implemented and put in the market quickly. When one of these initial versions starts shipping in higher volumes the development of an optimum VCAA is economically justified. In other words, the investment in optimizing will not be made until the market justifies it. Development of and an optimum VCAA is straight forward process of removing all unused tiles. This brings cost down to levels close to full custom, but maintains via configurability. If production volumes start to ramp up further, it is possible to make a full custom device by extracting and using only the needed cells from the VCAA. Figure 15 shows the common price versus volume curve indicating the best VCAA for each stage in the life of an ASIC.
Figure 15: Unit cost versus production volume for the VCAA development approach.
One of the benefits in using the VCAA development approach is there is always a via-configurable version available to go back to at anytime in the future. If changes are required or a customer wants a special version, it only takes a new via layer. And all of this can be done in less time, and for much less cost, than it takes to design a full custom device using the traditional method.
 J. Kemerling, M. Turner, and R. Wender, “Structured Analog IC Design Example using Mentor Graphics tool flow”, U2U, 2006.
 J. Kemerling, C. Hopper, and D. Ihme, “Structured Analog ASICs using the Mentor Graphics tool flow”, U2U, 2005.
 Tyson S. Hall, “Field-Programmable Analog Arrays: A Floating-Gate Approach.” PhD. Dissertation, Georgia Institute of Technology, July 2004.
 B. Cox, P. Dewell, D. Mavis, P. Eaton, and J. Kemerling “One-Mask Structured ASIC Technology for Cost Effective Radiation Hardened ICs,” GOMAC Tech, 2005.
 R. Gregorian, K. W. Martin, and G. C. Temes, “Switched-Capacitor Circuit Design,” Proceedings of the IEEE, pp. 941-966, August 1983.
 R. Wender, “How to Design a 16 bit Sigma Delta Analog to Digital Converter,” Application Note TSA002, Triad Semiconductor, Inc., January 2007.
 Mingliang Liu, Demystifying Switched Capacitor Circuits, Elsevier, Burlington, MA, 2006.
 J. Kemerling, “Semi-Custom, VIA-Configurable Analog and Mixed-Signal ASICs,” GSA Forum, March 2009.