Analog IC design has long been considered “full-custom only.” In this paper via-configurable analog/mixed signal technology is introduced as a means for resolving the critical issues confronting analog/mixed signal IC designers—cycle time and tooling cost. The method for developing and configuring via configurable arrays (VCAs) using a single via layer is described. Finally, the VCA design process and how VCA technology provides a path to full-custom solutions with much lower risk and lower overall cost is explained.
In 1965 Gordon E. Moore published a paper called “Cramming more components onto integrated circuits.” In this paper Mr. Moore documented his observation—the number of transistors on a single chip has doubled about every two years. Five years later Carver Mead gave him credit by referring to Moore’s observation as “Moore’s law.” 
Today semiconductor companies seem to be driven to comply with this trend—a self fulfilling prophecy. Of course once integrated circuit geometries get to atomic levels, the Moore’s Law era will be over. There is a lot of speculation when this will occur, but somewhere between the next 15 and 50 years seems to be the general consensus.
The less well known “Moore’s second law” states as geometries shrink exponentially, manufacturing costs increase exponentially. It should more accurately be called “Moore’s first corollary” since it is a natural consequence of “Moore’s law” and we just have to live with it whether we like it or not. Some go so far as to say economics will halt Moore’s law before physical limitations. 
As a result of Moore’s law, application specific integrated circuits (ASICs) have become much more complex and cost a lot more to make. Consequently, fewer are being developed every year. Maybe there should be a Moore’s second corollary which would go something like “as the number of transistors doubles, the manufacturing costs also double, resulting in half as many ASIC starts.”
Moore’s law does not apply to analog IC design. Many analog chips are still designed in processes with a minimum feature size greater than 0.18 micron. Even 0.18 micron designs rarely use channel lengths less than 0.5 microns. Accordingly, no matter how small the geometries go, analog has tended to stay about the same size or shrink at a much slower rate than the digital. Mixed signal devices, where some analog circuitry is required on the same substrate as the digital, present very difficult problems for the analog IC designer. A simple analog-to-digital converter consisting of less than 1000 transistors can consume as much area as 100,000 logic gates.
In the same way most semiconductor foundries push the envelope to cram more transistors into a single chip; the electronic design automation (EDA) industry has focused most of their efforts on tools for the digital engineer. Analog designers basically do it the way they’ve always done it: 1) draw a schematic, 2) turn this into a SPICE compatible netlist, 3) simulate with a SPICE compatible simulator, 4) do manual layout of the circuit down to the transistor level, 4) check the layout for design rule violations, 5) check the layout versus schematic, 6) rerun simulations with some parasitic inserted on critical nodes (time permitting) and 7) tape out. After the design comes back from the fab, the designer finds out how well the SPICE models correlate with reality. Frequently this results in the need for a second pass, and sometimes a third, and hopefully not a forth, but it happens. This can be expensive particularly when using deep sub-micron processes.
A better alternative could be semi-custom analog IC’s. Field programmable analog arrays (FPAA’s) have shown some promise, but have not taken off for a variety of reasons. Of the FPAA approaches, the floating gate technique does offer some hope, but still has not made it to the mainstream. Even if it does, its primary purpose will be in prototyping—analogous to the ubiquitous field programmable gate array (FPGA) for digital circuits . By definition, field programmable devices cannot be identical to mask programmable or full-custom devices. In other words, field programmability comes with significant overhead making volume production less practical.
In addition to field programmable approaches, there have been attempts at mask programmable mixed signal and analog arrays where the device is configured for a particular application in the final metal layers. To date the layout has been a manual exercise which has proven to be very time consuming and error prone.
A new analog array concept has been developed where a place and route tool can be used while maintaining performance comparable to full-custom IC’s. This concept is based on a digital structured array approach where a single via layer is used to configure an entire device. These new devices are referred to as via configurable arrays (VCAs.) VCA’s will not take the place of FPAA’s or full-custom ASICs, but are a reasonable alternative for many small to moderate volume applications, see Figure 1
Via Configurable Technology 
VCA’s, like digital structured ASICs, have their origin in digital gate arrays. Gate arrays were first used in production in the late 70’s. According to Wikipedia (i.e. in someone’s opinion), “Gate Arrays were the predecessor of the more advanced Structured ASICs; unlike Gate Arrays, Structured ASICs tend to include predefined or configurable memories and/or analog blocks.” Regardless of whether they are called Structured ASICs or gate arrays, their advantage comes from requiring fewer masks than a full-custom chip for customization. The VCA is a structured ASIC requiring only a single via layer for customization.
Most presently available semiconductor technologies have between four and eight metal layers. A via layer in the midst of these metal layers is ideal for configuration, allowing access to the metal layers above and below for routing without blocking signal tracks. Consequently, all the routing tracks are pre-defined (not created by an automated router) forming a via-configurable routing fabric. This is essential for semi-custom analog—the EDA companies have not been able to effectively replace an analog layout expert. In a via-configurable array, the routing fabric is created manually—the place and route tool only can place vias in the locations dictated by the routing fabric.
Figure 2 is a simplified illustration showing the process of configuring a VCA fabric. Figure 2 (a) shows the fabric with no vias, notice the fabric is made up of quadrants with each quadrant having routing tracks that are perpendicular to the routing tracks on the same metal layer in the adjacent quadrant. This minimizes the use of available routing tracks. Figure 2 (b) shows the fabric with vias placed. Figure 2 (c) shows which tracks are used and symbolic representation of some components in the base array connected to the fabric. The unused tracks in the fabric can be used for shielding. Notice analog circuit blocks are connected to the fabric through the lower metal layer. Ultimately the only layer used to configure the entire VCA is a single “configurable via layer” (CVL) between the two metal layers of the fabric.
The VCA concept can be used across an entire chip or just in certain sections. For instance, it may be most effective to do a full custom layout on sections of the chip that are well understood and not likely to change, but there may be other sections that need to change to support different customer requirements. Any section of a chip that is likely to change over time is an ideal candidate for via configurability.
The new paradigm for analog and mixed signal ASICs
In the initial phase of an ASIC project a VCA can be used which has more than enough resources to accommodate the ASIC requirements. This allows multiple versions to be implemented and put in the market quickly. Once one of these initial versions starts shipping in higher volumes the development of an optimum VCA can be justified. In other words, the investment in optimizing will not be made until the market justifies it. Development of and an optimum VCA is straight forward process of removing all unused resources. This brings cost down to levels close to full custom, but maintains via configurability. Finally if production volumes start to ramp up further, it is possible to make a full custom device by extracting and using only the needed cells from the VCA. Figure 3 shows the common price versus volume curve indicating the best VCA for each stage in the life of an ASIC.
One of the benefits in using the VCA approach is there is always a via-configurable version available to go back to at anytime in the future. If changes are required or a customer wants a special version it only takes a new via layer. And all of this can usually be done in less time, and generally for much less cost, than it takes to design a full custom device using the traditional method. With wafers staged at the fab, cycle times can be reduced to a few weeks.
VCA technology presents a new way to develop mixed signal and analog ASICs with significantly lower risk, lower cost, and less time than traditional approaches. VCAs are not a replacement for the full custom approach or FPGAs/FPAAs, but rather a supplement to them. In a typical product life cycle, field programmable devices are ideal to prove the concept, next a VCA can be utilized to develop a product that is suitable for production, once volume ramps up the device can transition into an optimal VCA, and finally when it makes it into the next cell phone or iPod it can move to a full custom ASIC. This approach is a practical way to develop ASICs regardless of mask costs.
About the Author
Jim Kemerling is the Chief Technical Officer of Triad Semiconductor. At Triad he is responsible for VCA technology development and implementation. His background includes over 25 years of experience with mixed-signal integrated circuit design and system-level development. Jim holds two patents and has published numerous papers. He received his Bachelor of Science in Electrical Engineering from South Dakota State University and his Masters in Electronic Engineering from the University of Nevada. Jim can be reached at firstname.lastname@example.org or 336-774-2150.
- Gordon E. Moore, “Cramming more components onto integrated circuits,” Electronics, April 1965.
- Sumner Lemon and T. Krazit, “With chips, Moore’s Law is not the problem,” Info World, April 2005.
- Tyson S. Hall, “Field-Programmable Analog Arrays: A Floating-Gate Approach.” PhD. Dissertation, Georgia Institute of Technology, July 2004.
- J. Kemerling, “Via Configurable ASICs for Analog and Mixed Signal Applications,” SoC Central, June 2006.