My name is Reid Wender. Here at Triad Semiconductor my title is “Manager – MSSA Design” but my friends just call me the Triad Evangelist.
What is MSSA Design you ask?
Mixed Signal Structured Array (MSSA) from Triad Semiconductor (site)
Triad Semiconductor makes the world’s only Via-Programmable Mixed Signal Structured Array.
Okay, but I still want to know what a MSSA is?…
Okay, let me back up…
ASIC or Application Specific Integrated Circuit, semiconductor, IC, or just ‘chip‘ are common names for miniature electronic designs placed on small pieces of Silicon. Well, I’ve been making these ‘chips’ for over 17 years and we have kept adding more and more transistors to these chips every year. In fact, there is a law (sort of) in our industry known as “Moore’s Law”, after Mr. Moore of course, that states that roughly every 18 months to 2 years you can put twice as many transistors in the same area of Silicon. This doubling of transistors per unit area is achieved by reducing the “feature size” of the transistors on the Silicon every 18 months or so. Back when I started digital ASIC design we were designing a 1.2 microns (micro meters) for features sizes. Over the past 20 years feature sizes have decreased (every 18 months or so remember) down to 1.0 micron, 0.7, 0.35, 0.25, 0.18, 0.13, and now 0.09 microns or 90 nano-meters as we like to say.
All this advance in technology and reduction in feature size is great for cramming more transistors and logic gates on to the same sized piece of Silicon.
Let me digress for a second – This is why electronics products keep getting cheaper over time. Every couple of years Intel and others are able to put out computer chips that are twice as fast and less expensive than previous generations.
Back to our story…
Feature size reduction is great for packing transistors onto Silicon but the downside is that as the feature size of the transistors get smaller the process required to make the ICs gets more and more expensive. In the old days you could get a 1.0 micron chip produced for $40,000 (we call it fab’ed – short for fabricated). Well todays 0.13 micron mask sets cost $800,000 (yep there is an extra zero in there).
Lots of companies have trouble forking over $800K to make a chip. Why does it cost $800K for a 0.13 micron fab versus $40K for a 1.0 micron fab. Well, a lot of the cost is in the “Mask Set” the mask set is a group of reticules that are used to expose the Silicon wafer to create the various layers of a semiconductor that make it act like transistors and logic gates. Many CMOS fabrication processes require 20 mask layers. As the features sizes get smaller and smaller the precision and time required to make each mask goes up.
Somebody, had the great idea that if you could reduce the number of masks required to make an ASIC you could reduce the fab cost. In fact, if you could make an ASIC with only ONE MASK LAYER you could reduce the cost by about a factor of 20. Instead of spending $800K on masks for a 0.13 micron chip you could then fab the chip for $40K.
Great idea but how do you do it?…
Now, I’ll tell you about Structured Arrays
A structured array is a semiconductor with 19 of the 20 layers of the chip predefined with logic gates, memory, and routing. The one undefined layer or the layer that the customer defines is the via layer. This via layer allows vias (fancy name for a metal to metal connection in an ASIC – actually more complicated than that but this is a good definition for our discussions) to connect different transistors and logic gates to each other to form logic circuits. When it comes time to fabricate the chip the via layer mask is produced, and the chip fab’ed.
(more on structured arrays next time and we haven’t even touched MSSA yet…)