Triad Mixed Signal Design Flow
The Triad Via-Configurable Array (VCA) design flow utilizes industry-standard front-end development and simulation tools. Configurable mixed signal ASIC technology combined with Triad's No-Full-Custom methodology removes the need for expensive back-end layout, place & route, and physical extraction EDA software therby greatly reducing development time and mitigating risk. By building applications upon the silicon-proven mixed-signal IP contained within Triad VCA platforms the designer can focus on their design instead of tweaking low level functions to get them to work with a particular foundry process.
ANALOG DESIGN
Analog circuitry is captured using industry-standard schematic capture tools and Triad's symbol library representing analog tile primitives such as OTAs, OpAmps, resistors, capacitors, switches, etc? Higher complexity macros and IP blocks such as Digitally Controlled Amplifiers (DCA), Filters, ADCs, and DACs are placed in schematics using pre-defined Triad macro symbols. Triad delivers to the customer a Mixed-Signal Design Kit (MDK) containing symbol libraries and Spice macromodels. The MDK is available in a Mentor version and a general-purpose version. The Mentor-MDK contains a complete symbol library for use with Mentor's Design Architect schematic capture software. The general-purpose version of the MDK contains the Spice macromodels and transistor models for the Triad primitives without schematic capture symbols. Users can create their own symbol libraries to utilize their existing schematic capture tools to execute Triad designs.
ANALOG SIMULATION
Analog functionality is verified through Spice simulation. Each analog element is supported with low-level and macro-model Spice information. By utilizing standardized models, the analog functionality can be easily simulated on a wide range of Spice simulators.
LOGIC DESIGN
The Triad digital library is optimized for HDL synthesis. Digital designs are captured in Verilog, VHDL, or schematics or any combination of the three and simulated by standard Verilog/VHDL simulators. The VCA Design Kit (MDK) contains simulation and synthesis libraries for the leading simulation and synthesis tools. RAM and ROM generation, configuration, and simulation models are generated by Triad's memory generator software. The MDK contains digital library symbols for Mentor's Design Architect schematic capture software. The symbol libraries, synthesis libraries, simulation models, and memory generator models are provided in the MDK.
MIXED SIGNAL SIMULATION
The analog and digital sections may be combined for mixed signal simulation. Mixed signal simulation requires a mixed mode simulator capable of HDL and Spice simulation in a co-sim environment.
POST SYNTHESIS
Triad provides the user with synthesis libraries. The user performs digital synthesis to create a structural Verilog netlist representing the digital, memory, and I/O portions of the design. Scan insertion and ATPG are performed by the user on the synthesized digital netlist. Triad software is executed by the user to convert the Spice netlist representing the analog portion of the design into a structural Verilog netlist. The analog and digital structural Verilog netlists are then combined into a single Verilog netlist representing the entire design.
VIA-ONLY PLACE & ROUTE
Triad accepts as input the merged analog and digital netlist in structural Verilog format. The merged netlist plus I/O placement, timing constraints, and placement constraints are input to Triad's via-only place & route software. The Triad place & route software places the analog and digital instances from the user's netlist onto the available resources of the platform. The software then configures the primitives and interconnects the primitives by placing vias into the routing fabric that is overlays the entire VCA platform. The place & route software outputs a GDSII layer representing the via layer between metal-2 and metal-3 along with digital delays files and analog parasitic files. Triad's place & route plus extraction requires under 30 minutes for the VCA-1 platform.
POST-LAYOUT SIMULATION
The post-layout digital delay files are provided to the customer for static timing analysis and back-annotated digital simulations. Additionally, the extracted parasitics are also provided to the customer for post-layout analog Spice simulations. Once the customer is satisfied with post-layout timing and simulation results, the customer and Triad perform a Critical Design Review (CDR). Following a successful completion of the CDR, the design is released to fabrication.
FABRICATION
The GDSII for the via layer is released and a single reticle is created. This reticle is processed against staged wafers at the foundry and packaged prototypes are then provided to the customer 4 weeks after the tapeout to fabrication date.
ENGAGEMENT MODEL
Triad supports a variety of customer engagements from Triad providing turn-key design from the customer's specification to Triad accepting post-synthesis, post scan insertion gate-level netlists from the customer. On the delivery side, Triad can provide the customer with packaged/tested parts, bare die, or configured wafers. For more information about working with Triad, to request a quotation, or to have Triad Applications Engineering review your design contact Triad at inquiry@triadsemi.com or call (336) 721-9450.
