Triad Semiconductor

Introduction

As any ASIC designer knows all to well, the pressure is relentless to develop larger chips with more functions (including analog) and to deliver in record time. Fabs keep making smaller geometry processes which allows for more transistors per unit area, but this does not make the design easier. And then there is the cost of a mask set, which also continues to escalate to unbelievable levels. The cost of a single transistor layout error can cost 100’s of thousands of dollars. In other words, first pass success is mandatory. EDA tools are improving (this improvement is not free) but the EDA vendors can not make an absolute guarantee a chip will be error free. So what is the solution? Quit designing full-custom ASICs. Start using Via-Configurable ASICs (VCAs.)

Via-Configurable ASICs

Gate arrays have been used successfully in digital applications for decades. The benefits of gate arrays came from having fewer custom layers, allowing masks to be shared between designs. As you would expect, these benefits are maximized when the number of custom masks is minimum. The FPGA came along and actually eliminated mask costs all together. However, as anyone who has designed full-custom ASICs and used FPGAs knows, field programmability does not come without significant overhead. In other words, the FPGA has not made the custom ASIC obsolete. So if an efficient design is needed, without the overhead of an FPGA, the mask configurable approach should be considered.

Of the available single layers that could be used for configuring an ASIC, a via layer is best suited. A via layer allows access to the metal layers above and below for routing without blocking signal tracks. This allows all the routing tracks to be pre-defined meaning the ASIC is completely configured by the placement of vias. The idea of using a via layer to completely configure an ASIC [3] was first suggested in the 1980’s, however, successful implementation has stalled, until recently, due to the lack of suitable place and route tools.

Via-Configurable Analog

Semi-custom analog design has been attempted several times dating back to the mid-80’s. These attempts were largely unsuccessful due to the need to manually interconnect the base array analog cells. For purely digital stuff it is relatively easy – just use a place and route tool. For analog, this is not practical. In almost all cases, analog has required full-custom layout. Full-custom layout is time consuming and error prone. The benefits of VCAs come from having fewer custom masks per design, allowing masks to be shared between designs. With all the metal routing predefined, it is feasible to use place-n-route technology for analog circuits.

Triad Semiconductor’s, patent pending Via Configurable Array (VCA) technology, brings the benefits of digital gate arrays to analog and mixed-signal design. The VCA solution allows designers to create mixed signal ASICs using a single via layer without full-custom layout.

The Routing Fabric

An example of a VCA built in a four metal layer process uses metal 2 and metal 3 arranged as shown in Figure 1(a) to form the VCA fabric. Notice the fabric is made up of metal 2 and metal 3 tracks that are alternately rotated 90 degrees to minimize the length of routing tracks used for interconnect.

(a)

(b)

(c)

Figure 1: The VIA configurable fabric (a) with the used tracks and via locations (b) and only the VIA layer (c).

The vias are then placed to define the tracks used in a given fabric square, see Figure 1(b). Finally, Figure 1(c) shows only the vias needed for the new via layer required to define the ASIC.

Shielding Analog Signals

As any analog IC designer can attest, noise is an issue in any analog or mixed signal design. In full-custom design, judicious use of guard-banding, shielding and white space is employed in an attempt to minimize the adverse effects of noise generated by digital circuits or other analog signals. In the VCA, all unused routing fabric can be used for shielding. Figure 2 illustrates the use of adjacent unused metal 2 runs used in conjunction with a predefined metal 1 shield and unused metal 3 tracks to form a three dimensional shield around two metal 2 signal tracks.

Figure 2: Shielding of analog signals.

Analog Tile

The analog portion of a VCA is made up of several analog tiles. Each tile contains several components typically used in an analog IC. Figure 3 is an example of a floor plan for an analog tile that contains two OTAs, an output stage (cascade with an OTA to make an opamp), capacitor and resistor arrays, analog switches, a transistor array and logic (normally used for clock generation.)

Figure 3: Analog tile floor plan.

This particular analog tile is optimal for single-ended switch capacitor (SC) filter designs.

Figure 4 shows an array of 12 analog tiles. The analog tiles are oriented so the logic and switches are facing the “digital channels.” The digital channels are used to carry clock or control signals from the digital section. Notice the “fixed analog” block in the center of the array. This is where frequently used analog functions are placed (e.g. band-gap reference.)

Figure 4: Analog tile array with routing channels.

Logic Tile

The digital portion of a VCA is consists of logic tiles that are composed of logic cells. An example of a typical logic cell contains four NAND gates, two muxes, one D-type flip-flop and ten inverters as shown in Figure 5. A single logic cell is equivalent to approximately 11 gates. A full logic tile contains 128 logic cells and 256 bytes of single port SRAM.

Figure 5: Logic cell.

VCA Design Flow

The VCA design flow, shown in Figure 6, allows for entry at virtually any point in the development process. In other words, a customer can specify a turnkey ASIC or actually manipulate the physical via location or anywhere in between. A design can be prototyped in field programmable devices and off-the-shelf-components. When the prototype is verified it can be converted to a VCA with minimal modification.

Figure 6: VCA design flow.

It should be noted, the VCA design flow is absent of layout (polygon editing) and layout verification (DRC). This is due to the fact that the VCA platform has already been completely verified prior to production release. Hence, the VCA designer is able to focus on design capture and simulation.

Switched Capacitor Filter Example

A switched capacitor filter is an excellent fit for a VCA. Specifications for a 4^th order SC filter are listed below.

Table 2: Unit capacitors required for H₁(z).

Table 3: Unit capacitors required for H₂(z).

It is important to note the capacitors that are not integer multiples of unit capacitors are composed of units plus remainders. In the case of C14, it is made up of 81 units plus a remainder of 1.3. The total number of units used in H₁(z) is 174 plus a 1.3 remainder. H₂(z) uses a total of 122 units + remainders of 1.1, 1.8 and 1.8. The total number of units plus remainders fits well within the available resources of two analog tiles.

The clocks required for the switched capacitor filter would be generated in the digital section of the VCA. Typically, switched capacitor filters require two-phase non-overlapping clocks. Hence, the analog tile contains some logic, which can be used to generate multiple phases locally. This keeps the number of signals that must be run from the digital section in to the analog section to a minimum.

10 bit Successive Approximation ADC

Analog to digital converters using a successive approximation register (SAR) are commonly used for signal quantization with sample rate requirements less the 1 MS/s. SAR ADCs can be easily implemented using available fixed analog blocks, analog tiles, and logic tiles from a VCA. Figure 9 shows a simplified block diagram for a 10 bit SAR ADC.

1. J. Kemerling, M. Turner, and R. Wender, “Structured Analog IC Design Example using Mentor Graphics tool flow”, U2U 2006.
2. J. Kemerling, C. Hopper, and D. Ihme, “Structured Analog ASICs using the Mentor Graphics tool flow”, U2U 2005.
3. B. Cox, P. Dewell, D. Mavis, P. Eaton, and J. Kemerling “One-Mask Structured ASIC Technology for Cost Effective Radiation Hardened ICs,” GOMAC Tech, 2005.
4. R. Gregorian, K. W. Martin, and G. C. Temes, “Switched-Capacitor Circuit Design,” Proceedings of the IEEE, pp. 941-966, August 1983.
5. Triad Semiconductor, Inc.,http://triadsemi.com.