Triad Semiconductor's Via-Programmable,
Mixed Signal ASIC Technology
Triad's mixed signal platforms enable the design of analog and digital circuitry on a single semiconductor die with only one fabrication mask.
Silicon Wafer Processing
For those visitors unfamiliar with the chip fabrication process, all ICs (including application specific ICs or ASICs) are built up in as many as 8 or more layers at the foundry, i.e. the chip factory. They all begin as part of a silicon wafer on which electronic processing elements and their interconnections are fabricated. The placing of these miniature features on the silicon die is achieved through photolithographic masks and a variety of processing steps. The 200+ processing steps required for modern ICs fall into four general categories, specifically deposition, removal, patterning, and modification of electrical properties. Each layer requires one or more masks and a number of processing steps to define which circuit features are to be included in that layer of the chip and where they are to be placed.
Moore's Law
Every 18 months or so over the past 40 years, chip manufacturers have been able to pack twice as many transistors into the same area of a silicon chip due to the reduction in feature size. This area efficiency improvement over time is known commonly as "Moore's Law". This law coupled with the use of increasingly larger wafers has been the driver behind achieving more complex and less expensive digital ICs over the past two decades.
Deep Sub-Micron Problem
As semiconductor geometries have progressed into the region known as Deep Sub-Micron (DSM), which is generally regarded as 0.18 microns (180nm) and below, ASIC fabrication costs have skyrocketed. It's now to the point where a complete mask set and fabrication for a 130nm or 90 nm design can be well over 1 million dollars. In combination with the even higher cost of designing the chip, the investment needed just to get to the first sample of an ASIC has become a barrier for many groups to pursue a custom silicon solution.
Digital Structured ASICs
One alternative to the rising cost of ASIC development in the DSM era has been the introduction of Structured Array or Structured ASIC technology. A Structured ASIC pre-diffuses logic, memory, and I/O elements into the majority of layers used to define an IC. The designer is given access to some of the metal and via layers to customize or configure their design onto the structured array. A CMOS process requiring say 20 masks to define an IC in a full-custom process may only require 1 to 4 layers of customization in a structured array approach. The pre-diffused structured ASIC platform can be manufactured ahead of time and staged at the foundry resulting in greatly reduced fabrication time. The use of the same platform to support a number of customers allows the platform development cost to be amortized over many different applications.
By using structured arrays, companies benefit from reductions in:
- Mask Costs (by a factor of 10x to 20x)
- Place & Route Time
- Fabrication Time
- Overall Project Cost
Mixed Signal Structured Arrays (MSSAs)
Triad Semiconductor brings the benefits of structured arrays to mixed signal IC design. This is the first time that another approach to analog or mixed signal chip development has ever been available as an alternative to a costly, risk prone, full custom methodology or, for that matter, a discrete board level implementation. Triad Semiconductor's MSSAs are positioned to address underserved if not ignored markets.
In MSSA technology, analog and digital circuitry are pre-diffused into the die and a single mask layer, namely the via layer between metal 2 and metal 3 routing layers, is used for application specific wiring, i.e. component interconnections.
Using a MSSA platform, a complete analog and digital IC can be design in a fraction of the time required for traditional methods and at much lower costs. MSSA technology brings the benefits of digital structured ASICs to analog and mixed signal design:
- Reduced Overall Project Cost
- Mask Costs Reduced by 20x
- Simplified Fabrication - only 1 mask layer required
- Reduced Fabrication Time
- No Full-Custom Layout Time, Tools, or Expenses Required
- Reduced Place & Route and Physical Verification Time
- Access to Reusable Analog IP (industry first)
- Greatly Reduced Risk of Re-spins
Learn more about Mixed Signal Structured Array Technology...
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