Introducing Mixed Signal ASICs by Triad Semiconductor

Triad Semiconductor (TRIAD) delivers mixed signal IC solutions using a radically different approach that allows you to integrate analog and digital circuitry into an application specific integrated circuit (ASIC) at a fraction of the cost and time normally required.

TRIAD’s approach to IC design is inherently faster, less expensive, safer and simpler than any other approach in the market.

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To IP or Not to IP

Although all real engineers would like to create all of their designs from scratch, that just is not practical in today’s fast-paced ASIC development world. The need to integrate intellectual property (IP) from third-party providers is the reality.

Engineers are also realizing that convergence is real in the ASIC world. More and more ICs are requiring the integration of digital and analog functions onto the same device. Today’s applications need digital processing coupled with analog to digital converters (ADC), digital to analog converters (DAC), PLLs, op-amps, analog filters, voltage regulators, and on and on. Even seemingly digital communication links such as USB and FireWire contain sophisticated mixed-signal physical interface (PHY) circuits. On the digital side, designers must develop or integrate communication links, microcontrollers, memory interfaces, DSP processing, and local control circuitry.

To add to the integration problem, there are not many ASIC designers that are equally well versed in both analog and digital design. Instead most are either 90% analog and 10% digital or 90% digital and 10% analog. Actually, for the digital engineers, many are 99% digital and 1% analog, but that’s a different article. (If you think you are a 50/50 or even a 60/40 designer then send me an e-mail – I would like hear from you).

The complexity of these varied development requirements coupled with time-to-market pressures force companies to consider integrating IP blocks from third-party suppliers. Advances in mixed-signal via-configurable array (VCA) technology are enabling analog soft-IP integration that emulates the rapid, efficient, and cost effective IP use found in all-digital FPGAs.

Digital IP – Difficult but Doable

When companies realize that they cannot develop all of the IP needed for an ASIC in a timely and cost effective manner, the search for third-party IP begins. In theory, digital IP has always been available in the form of GDSII layout blocks representing a particular function. Such blocks have constrained, or ‘hard,’ features–including aspect ratio, power and clock routing, internal timing, power consumption–and they are tied to exactly one process at one integrated chip (IC) foundry. With all of these fixed or hard parameters, this type of IP block has often been referred to as ‘hard IP,’ where ‘hard’ meant fixed parameters as well as hard to work with.

Digital IP sharing became widespread when designers advanced up from physical design and even schematic capture to the more interchangeable design format of a hardware description language (HDL). The adoption of Verilog and VHDL HDLs coupled with synthesis electronic design automation (EDA) tools enabled designers to express designs in a format independent of foundry, ASIC vendor library, and EDA toolset. Functions described in an HDL no longer had the fixed constraints of hard IP. An HDL IP block could be modified by synthesis to optimize its aspect ratio, timing, power, and routing resources and, most importantly, the IP was no longer tied to a particular process or foundry. The relaxation of constraints that HDL-based IP required led many to describe this new IP exchange format as ‘soft IP.’

The widespread use of HDLs and soft IP makes interchange of digital IP technically feasible but integrating someone else’s IP can be a significant effort. Once a company decides to use third-party IP many different factors must be evaluated and many of them, as shown in , are not technical issues. Many companies find that a considerable amount of time and cost is associated with evaluating and integrating third-party IP.

Table 1 – Factors companies consider when integrating digital IP

The FPGA Guys – Easy to use Free IP for the Masses

There’s a dirty little saying in the EDA and IP business that goes something like ‘the best customer buys EDA tools and licenses IP and then goes out of business before ever using them.’ For the most part, the third-party IP business is setup like the EDA business, where vendors want to get all of their money on the front end. The exceptions to this approach are the FPGA companies that give away a lot of quality IP. Yes, the FPGA companies must pay for the development of their IP and pass the cost along to their customers as an increase in the silicon unit-price but since these costs are spread out across a large user base, the incremental costs are negligible. And, companies don’t pay for the IP until they are actually selling products and making money themselves. The FPGA approach focuses on removing the cost and integration barriers so that users can quickly get silicon to market and then the FPGA company makes money with the customer. FPGA vendor IP comes with a significant reduction in IP integration issues. The FPGA vendor provides consistent documentation, integration support, and a uniform development flow. By making IP easy to use and eliminating large up-front charges, FPGA products have captured a significant part of the IC market that was historically dominated by ASICs.

Analog IP Stumbling Blocks

Digital IP is a necessary part of IC development. And the FPGA IP distribution model really works. So, what is the state of analog IP? Simply put, analog IP is hard to use. Analog IP comes with all of the evaluation and integration issues associated with digital IP plus a set of issues unique to analog. Analog IP is provided as hard IP in the form of GDSII layout blocks. These blocks are fixed in size, tied to a particular foundry and process, and they are often difficult to integrate. Getting rid of noise problems from nearby circuits is often a problem due to the fixed layout of the circuits within a hard IP block. Integrating high performance analog IP with high speed digital logic on the same complementary metal-oxide-semiconductor (CMOS) die is a science and an art that, for even the best design teams, requires multiple fabrications at the foundry.

Soft IP for the Analog ASIC – Impossible yet True

What if designers could use analog IP the way they use digital IP from FPGA companies? What is needed is a framework and integration method that allows developers to easily integrate mixed-signal building blocks into complete designs. Digital IP sharing and FPGA use became pervasive as designers moved up in abstraction from physical or full-custom design. Sure, higher levels of design abstraction are slightly less efficient but companies have reaped such benefits from this approach that it is difficult to find many people doing full-custom digital design these days. If mixed-signal soft IP could be provided by an ASIC company free of charge, then companies could adopt a get-to-market-quickly approach without paying large up-front licensing fees and spending effort on third-party IP evaluation.

If a configurable approach could be brought to mixed-signal development, then analog designers could more easily reuse designs and share IP. Via-configurable array (VCA) technology incorporates silicon-proven analog and digital resources on a single semiconductor die. These resources are then covered with a global routing fabric that can be completely configured and interconnected with a single fabrication mask change, as shown in Figure 1.

Figure 1 – VCA global routing fabric configured by auto placing vias to interconnect resources

Maybe some analog designers reading this are thinking “every polygon and transistor must be hand-crafted to make an elegant design.” And, for the few cases where this is true, analog designers should stay with full-custom layout. For the vast majority of designers, however, having a set of silicon-proven configurable mixed-signal building blocks plus free mixed-signal IP would result in a real productivity improvement.

The History of Analog Arrays – Size Does Matter

In the past, configurable analog arrays consisted of either “fine-grain” or “coarse-grain” approaches. The fine-grain solutions consisted of a sea-of-transistors that could only be manually interconnected by customizing the metal and via layers of the device. This approach worked for very small analog-only designs but the routing complexity associated with this method prohibited this architecture from scaling to larger designs or designs that contained any appreciable amount of digital. The manual selection of transistors and routing also severely limited IP reuse in these architectures. The course-grain approaches consisted of large analog blocks that were configured as a limited number of macro functions such as low-pass filters or data converters. The parameters on the filters and converters could be adjusted but the large blocks could not be decomposed into smaller blocks to build other circuits. The course-grain solutions offered little flexibility and could not be used if the circuit did not match the platform macro resources.

Today’s Via-configurable Analog Arrays

Today’s configurable mixed-signal solutions, Via-configurable arrays, are built from “medium-grain” resources. Instead of being a sea-of-transistors or macro-function blocks, VCAs utilize tiles containing common analog resources that can be combined into a variety of circuits. VCA analog tiles contain operational amplifiers, buffers, and bias generators. In addition to these resources each analog tile contains arrays of capacitors, resistors, switches, transistors, and local logic, as shown in Figure 2.

VCAs are built from a variety of analog tiles optimized for single-ended, fully-differential, wide-band, lower-power, or high-voltage operation. These resources are the basic building blocks for a wide range of analog circuits such as: continuous time filters, switched capacitor filters, programmable gain stages, pulse width modulators, sigma delta modulators, analog to digital converters, and digital to analog converters. VCAs also contain high performance ADC, DAC, h-bridge, and power regulator tiles. Unlike traditional full-custom hard IP or the coarse-grained configurable IP blocks, these VCA resources are fully via-configurable, allowing them to be rearranged into other analog circuits as needed by the customer’s design using automated via-only place and route software.

Figure 2 – Mapping of an analog circuit to a via-configurable array

In addition to a fully configurable set of analog resources, VCA platforms contain digital tiles that combine logic and memory resources. These VCAs are capable of supporting high performance mixed-signal IP blocks and designs. Companies adopting VCA technology gain access to the rapid prototyping and production of mixed signal designs at a fraction of the cost of traditional full-custom development, yet with unit-pricing comparable to full-custom designs.

Creating Reusable Mixed-signal IP

Before IP can be reused, it must first be created. By comparing the VCA design process to the design process for a full-custom design, it becomes easy to see why VCA-based designs are easily reusable and why ease of design reuse is the essence of any viable mixed-signal IP concept. As shown in Figure 3, the ‘front-end’ portion of the VCA and full-custom design is identical. The first step is to split the design into analog and digital section. The digital portion of the design is captured as either an HDL or schematics, simulated, and synthesized into a gate-level netlist. The digital portion of the design is almost always captured as schematics and simulated with a SPICE-compatible simulator. Here is where the major divergence begins between the VCA and full-custom design flows.

Figure 3 – VCA flow facilitates soft IP reuse compared to full-custom’s hard IP output

Full-custom Layout

In a full-custom design, schematics and simulation are only rough models to guide the engineer in the “back-end” portion of the design. In the full-custom approach, the “back-end” portion of the design involves manually creating transistors and other circuit elements out of polygons in a layout editor. The “front-end” schematic database does not drive the layout process, instead the engineer acts as the manual synthesis, placement, and routing “tool” that creates every transistor and polygon in the design. Since all of the polygons and their interactions are new, the design must undergo physical extraction to determine the parasitics and couplings between adjacent and not-so-adjacent circuit structures. This parasitic/coupling analysis loop may require several iterations and is often a source of delay and increased expense in full-custom development efforts. Once the designer completes the “back-end” of the design, the output is a rectangular block of transistors with a rigid set of parameters that will be difficult to integrate or modify for future designs.

Via-configurable Arrays Enable Mixed-signal Soft IP

VCA architectures do not require full-custom layout because the mixed-signal resources are pre-placed along with a global routing fabric. The invention of analog-aware, via-only automatic place and route software allows the manual layout “back-end” to be replaced with an automated place and route “back-end.” Just as in digital design, where the HDL or schematic drives the synthesis and place and route process, the analog schematic and netlist in a VCA flow is the last manual step required to create a design or IP block. In the VCA flow, the digital gate-level netlist is merged with the analog SPICE-level netlist and this mixed signal netlist is the input to the via-only place and route software. As shown in Table 2, by capturing design intent at the schematic/netlist level, designers can create and reuse a wide range of mixed-signal IP blocks.

Table 2 – Reusable VCA mixed-signal soft IP

Designers can understand and integrate schematics and netlists much more readily than they can hard IP blocks. By providing designers with the ability to capture design intent in a “soft” format, VCA vendors will encourage the sharing and reuse of mixed-signal IP the same way that HDLs and synthesis enabled digital-only “soft-IP” reuse. Since VCA technology utilizes a single fabrication mask and requires no full-custom layout, the development time and cost, risk, and fabrication cost are reduced to the point that VCA development appears more like designing an FPGA than like the traditional full-custom endeavor. Like the FPGA companies, VCA providers are fabless semiconductor companies interested in selling silicon. As well as enabling customers to take advantage of with low development costs, VCA companies will encourage the use of their technology by providing low-cost development coupled with an ever-expanding and free mixed-signal IP library and with unit-pricing and performance on par with full-custom designs.

There are many reasons for the early demise of the digital structured ASIC market. A leading candidate is the market itself. The severe downturn in the economy led to depression-like times in the technology segment. ASIC starts went way down. Companies were not looking to spin a new ASIC. Most were happy to let designs grow old and age gracefully. Just as this perfect storm is forming, the push for structured ASICs takes life.

Digital ASIC companies have been trying to retain market share for years. FPGA offerings have continued to advance, taking over large segments of the ASIC market. Gate array ASICs had early success as customers were looking for cost competitive ways to convert from expensive FPGAs. The big FPGA companies, not willing to let their market erode, continued to expand their product and tools. Before long, the price advantage for conversions was gone. The FPGA-to-ASIC conversion market stagnated.

While continuing to support their core technology – cell-based ASICs – companies were looking for ways to regain market share. Enter structured ASICs. All the good stuff associated with gate array ASIC products – lower NRE, lower mask costs. None of the bad stuff associates with standard cell ASICs – long design time, significant design risk, high mask cost.

Digital Structured ASICs predefine most of the layers of an IC with pre-placed logic gates and memory. The user’s design is then configured and interconnected by customizing the last few metal layers. This simplified design and manufacturing process can yield lower cost and lowered risk. Technology size goes down, NRE goes up, ASP goes down. Overall cost, NRE + ASP is lower.

Early adopters wrote many articles predicting the potential size of the structured ASIC market. As late as 2004 it was predicted that the structured ASIC market would grow to $1.4B by 2008. Other predictions talked about a $2.5B market by 2009.

The structured digital ASIC provided a way for the ASIC guys to combat the standard product guys. With the advantages of faster time to market and a lower cost barrier, the early predictions of a robust digital structured ASIC market were understandable. Wrong, but understandable.

Mixed signal structured ASICs follow a similar technology path as their digital counterparts. Simply, they process analog and digital signals on a single chip. Until now, mixed signal ASIC design has required time consuming, expensive, and risky full-custom (manual) layout.

Using a structured approach with a mixed signal ASIC allows designers to create mixed signal ASICs using a single via layer. Full-custom layout not required.

The question is whether the downfall of the digital structured ASIC market is a leading indicator for the mixed signal structured ASIC market. If the underlying factors were the same, the answer should be the same. They are not. Here’s why:

When you lower the barrier of entry, namely NRE, you open up the ASIC possibilities to a new (and large) group of customers. Being able to prototype a device in the same technology that will be used in production is much more useful to designers than kluging together discrete digital and analog functions. Reducing risk by using IP blocks that have been silicon proven allows designers to implement functions that they know will work the first time. Reducing the time to go from design – to prototype – to production – gives companies looking to implement a mixed signal ASIC a competitive advantage.

You can buy a mixed signal FPGA. There are applications where a mixed signal FPGA will support your requirements. But, the possibility of solutions on the mixed signal side is much smaller than in the digital world. In the digital space, entire categories of ASIC devices have been eliminated by using an FPGA or ASSP. These alternatives offer no NRE, no risk and low unit price. That offering is much smaller in the mixed signal space. The mixed signal designer has fewer options from which to choose. Go the full-custom mixed signal ASIC route, meet your design requirements, integrate all the custom code and features that make your end product unique. Shoe horn your requirements into a standard product or mixed signal FPGA and loose some of the cool features that enable to sell your products at a high margin.

Or – give customers an option. The best of both worlds. Via-configured arrays. Structured mixed signal ASICs. A solution that truly fills the gap for the mixed signal ASIC designer. With history as a guide, mixed signal ASIC companies looking to provide customers with a viable solution should do just fine.

Visit Triad Semiconductor, www.triadsemi.com , for more information about Triad’s revolutionary via configurable array (VCA) technology that enables the rapid creation of low cost, low risk, rapid time to market mixed signal ASICs.

As any ASIC designer knows all to well, the pressure is relentless to develop larger chips with more functions (including analog) and to deliver in record time. Fabs keep making smaller geometry processes which allows for more transistors per unit area, but this does not make the design easier. And then there is the cost of a mask set, which also continues to escalate to unbelievable levels. The cost of a single transistor layout error can cost 100′s of thousands of dollars. In other words, first pass success is mandatory. EDA tools are improving (this improvement is not free) but the EDA vendors can not make an absolute guarantee a chip will be error free. So what is the solution? Quit designing full-custom ASICs. Start using Via-Configurable ASICs (VCAs.)

Via-Configurable ASICs

Gate arrays have been used successfully in digital applications for decades. The benefits of gate arrays came from having fewer custom layers, allowing masks to be shared between designs. As you would expect, these benefits are maximized when the number of custom masks is minimum. The FPGA came along and actually eliminated mask costs all together. However, as anyone who has designed full-custom ASICs and used FPGAs knows, field programmability does not come without significant overhead. In other words, the FPGA has not made the custom ASIC obsolete. So if an efficient design is needed, without the overhead of an FPGA, the mask configurable approach should be considered.

Of the available single layers that could be used for configuring an ASIC, a via layer is best suited. A via layer allows access to the metal layers above and below for routing without blocking signal tracks. This allows all the routing tracks to be pre-defined meaning the ASIC is completely configured by the placement of vias. The idea of using a via layer to completely configure an ASIC [3] was first suggested in the 1980′s, however, successful implementation has stalled, until recently, due to the lack of suitable place and route tools.

Via-Configurable Analog

Semi-custom analog design has been attempted several times dating back to the mid-80′s. These attempts were largely unsuccessful due to the need to manually interconnect the base array analog cells. For purely digital stuff it is relatively easy – just use a place and route tool. For analog, this is not practical. In almost all cases, analog has required full-custom layout. Full-custom layout is time consuming and error prone. The benefits of VCAs come from having fewer custom masks per design, allowing masks to be shared between designs. With all the metal routing predefined, it is feasible to use place-n-route technology for analog circuits.

Triad Semiconductor’s, patent pending Via Configurable Array (VCA) technology, brings the benefits of digital gate arrays to analog and mixed-signal design. The VCA solution allows designers to create mixed signal ASICs using a single via layer without full-custom layout.

The Routing Fabric

An example of a VCA built in a four metal layer process uses metal 2 and metal 3 arranged as shown in Figure 1(a) to form the VCA fabric. Notice the fabric is made up of metal 2 and metal 3 tracks that are alternately rotated 90 degrees to minimize the length of routing tracks used for interconnect.

(a)

(b)

(c)

Figure 1: The VIA configurable fabric (a) with the used tracks and via locations (b) and only the VIA layer (c).

The vias are then placed to define the tracks used in a given fabric square, see Figure 1(b). Finally, Figure 1(c) shows only the vias needed for the new via layer required to define the ASIC.

Shielding Analog Signals

As any analog IC designer can attest, noise is an issue in any analog or mixed signal design. In full-custom design, judicious use of guard-banding, shielding and white space is employed in an attempt to minimize the adverse effects of noise generated by digital circuits or other analog signals. In the VCA, all unused routing fabric can be used for shielding. Figure 2 illustrates the use of adjacent unused metal 2 runs used in conjunction with a predefined metal 1 shield and unused metal 3 tracks to form a three dimensional shield around two metal 2 signal tracks.

Figure 2: Shielding of analog signals.

Analog Tile

The analog portion of a VCA is made up of several analog tiles. Each tile contains several components typically used in an analog IC. Figure 3 is an example of a floor plan for an analog tile that contains two OTAs, an output stage (cascade with an OTA to make an opamp), capacitor and resistor arrays, analog switches, a transistor array and logic (normally used for clock generation.)

Figure 3: Analog tile floor plan.

This particular analog tile is optimal for single-ended switch capacitor (SC) filter designs.

Figure 4 shows an array of 12 analog tiles. The analog tiles are oriented so the logic and switches are facing the “digital channels.” The digital channels are used to carry clock or control signals from the digital section. Notice the “fixed analog” block in the center of the array. This is where frequently used analog functions are placed (e.g. band-gap reference.)

Figure 4: Analog tile array with routing channels.

Logic Tile

The digital portion of a VCA is consists of logic tiles that are composed of logic cells. An example of a typical logic cell contains four NAND gates, two muxes, one D-type flip-flop and ten inverters as shown in Figure 5. A single logic cell is equivalent to approximately 11 gates. A full logic tile contains 128 logic cells and 256 bytes of single port SRAM.

Figure 5: Logic cell.

VCA Design Flow

The VCA design flow, shown in Figure 6, allows for entry at virtually any point in the development process. In other words, a customer can specify a turnkey ASIC or actually manipulate the physical via location or anywhere in between. A design can be prototyped in field programmable devices and off-the-shelf-components. When the prototype is verified it can be converted to a VCA with minimal modification.

Figure 6: VCA design flow.

It should be noted, the VCA design flow is absent of layout (polygon editing) and layout verification (DRC). This is due to the fact that the VCA platform has already been completely verified prior to production release. Hence, the VCA designer is able to focus on design capture and simulation.

Switched Capacitor Filter Example

A switched capacitor filter is an excellent fit for a VCA. Specifications for a 4^th order SC filter are listed below.

Specification	Label	Value
Sampling frequency	fS	280 kHz
Filter type	LP	Low pass
Cutoff frequency	fCO	1 kHz
Order	n	4
Transfer function	H(z)
Reference	Units
C11	1
C12	1
C13	1
C14	82.3
C15	45
C16	45

Table 2: Unit capacitors required for H₁(z).

Reference	Units
C21	1
C22	1
C23	1
C24	34.1
C25	44.8
C26	44.8

Table 3: Unit capacitors required for H₂(z).

It is important to note the capacitors that are not integer multiples of unit capacitors are composed of units plus remainders. In the case of C14, it is made up of 81 units plus a remainder of 1.3. The total number of units used in H₁(z) is 174 plus a 1.3 remainder. H₂(z) uses a total of 122 units + remainders of 1.1, 1.8 and 1.8. The total number of units plus remainders fits well within the available resources of two analog tiles.

The clocks required for the switched capacitor filter would be generated in the digital section of the VCA. Typically, switched capacitor filters require two-phase non-overlapping clocks. Hence, the analog tile contains some logic, which can be used to generate multiple phases locally. This keeps the number of signals that must be run from the digital section in to the analog section to a minimum.

10 bit Successive Approximation ADC

Analog to digital converters using a successive approximation register (SAR) are commonly used for signal quantization with sample rate requirements less the 1 MS/s. SAR ADCs can be easily implemented using available fixed analog blocks, analog tiles, and logic tiles from a VCA. Figure 9 shows a simplified block diagram for a 10 bit SAR ADC.

1. J. Kemerling, M. Turner, and R. Wender, “Structured Analog IC Design Example using Mentor Graphics tool flow”, U2U 2006.
2. J. Kemerling, C. Hopper, and D. Ihme, “Structured Analog ASICs using the Mentor Graphics tool flow”, U2U 2005.
3. B. Cox, P. Dewell, D. Mavis, P. Eaton, and J. Kemerling “One-Mask Structured ASIC Technology for Cost Effective Radiation Hardened ICs,” GOMAC Tech, 2005.
4. R. Gregorian, K. W. Martin, and G. C. Temes, “Switched-Capacitor Circuit Design,” Proceedings of the IEEE, pp. 941-966, August 1983.
5. Triad Semiconductor, Inc.,http://triadsemi.com.