Target Platform: Mocha™-Family – ARM® Cortex™-M0 Configurable Arrays

Application: Complete Automatic Meter Reading SoC

The TM0X11 combines a high-performance ARM® Cortex™-M0 32-bit processor optimized for deterministic embedded applications with a precision data acquisition system to provide a complete automatic meter reading (AMR) solution on a single power monitoring SoC. The Cortex-M0 support 0.8 DMIPS / MHz and can operate at frequencies up to 40 MHz. The precision analog system on the TM0X11 supports multi-channel current and voltage measurements with 24-bit sigma-delta analog to digital converters.

Flexible – Via Configurable Architecture
The TM0X11 design is implemented on TRIAD’s Cortex-M0 mixed signal configurable array (Mocha-1). The Mocha-1 is a via configurable array (VCA) containing a highperformance hardened Cortex-M0 microprocessor subsystem and configurable analog and digital resources. The TM0X11 design can be modified and debilitative products created by a single, low-cost via-mask layer change with new prototypes available in 4 weeks after tape out.

 ARM Cortex-M0 32-bit Processor

The ARM Cortex-M0 is a highly optimized 32-bit processor targeting mixed-signal and SoC applications that sets new performance, power, and determinism standards for deeply embedded applications. 

• ARM Cortex-M0 32-Bit Core
  • Binary forwards compatible with Cortex-M3 and Cortex-M1
  • Dynamic Power for Dhrystone loop: 130 uW/MHz (1.8V, 25C)
  • Dynamic power half that of the Cortex-M3
  • 50MHz operation
  • 0.8 DMIPS/MHz 
• Hardware Multiplier 32 x 32 à 32 bits, single cycle
• Integrated system timer (SysTick) and corresponding exception
• AHB-Lite interface for instructions and data
• Low latency AHB (peripheral bus) access for external load / store operations
• Thumb-1 instruction set plus a subset of Thumb-2 instruction.
• Deterministic instruction timing
  • Fixed interrupt latency of 16 cycles
  • Support for hardware stacking and unstacking of a subset of registers on exception entry and return
  • Low overall ISR entry and exit latencies
  • Exception handlers can be written in C without the need for assembler stubs
  • Interruptible-load-store multipliers for low interrupt latency.
  • WFI / WFE instructions to enable low-power sleep modes.
• Interrupt Controller (NVIC)
  • Software control of each interrupt
    • 4-level priority configuration
    • Enable / disable
    • Pend and un-pend functionality
  • Support for both level-sensitive and edge sensitive interrupts
  • Dedicated non-maskable interrupt (NMI)
  • Closely coupled with processor core for efficient exception handling:
    • Support for late-arriving exceptions to avoid having to re-stack context
    • Support for tail-chaining to reduce interrupt latency by folding together exception exit unstacking and subsequent exception entry stacking to allow direct intro into the ISR
• CoreSight^TM Compliant debug solution
  • Low-pin count JTAG or Serial-Wire interface to the debugger
  • Debug Halt mode
  • Access to memory and memory mapped registers while the processor is running or halted
  • Debug access to processor registers while the processor is halted
  • Watchpoint comparators that allow data address and instruction address matching and masking functionality
  • Breakpoint comparators that allow instruction address matching
  • BKPT instruction to allow unlimited number of breakpoints to be set in RAM regions of code

If a design does not optimally fit on an existing VCA, TRIAD can quickly and inexpensively assemble a VCA optimized for the application out of TRIAD’s extensive IP library as shown in Figure 2.

An optimized VCA can contain exactly the resources required by a particular application including:

• Total number of logic gates
• Number of distributed RAMs
• Number of block RAMs
• Digital I/O
• Number and types of Analog IP Blocks
• Analog I/O

VCA Digital Capacity

The digital section of each VCA consists of an array of logic tiles. In TRIAD’s 0.18-micron process, each logic tile contains 2,800 NAND2 equivalent ASIC gates. The logic elements within each tile are high-performance, low-power via-configurable combinatorial gates and flip-flops. These logic tiles are arrayed to create digital logic capacities up to the values shown in Table 1. Each logic tile contains a distributed 128×32 2-Port SRAM (4096-bits). These RAMs can be combined to make larger composite RAMs.

1 – 0.18-Micron VCA Maximum Logic Array Sizes

Block RAM Support

In addition to distributed RAMs within each logic tile, block RAMs of various sizes and configurations can be added to an optimized array. RAMs of various sizes can be generated and placed in the VCA. RAMs can be configured as 1-port or 2-port devices with varying address depths and data bus widths per RAM.

Figure 1 – Power management Application Space

Portable Power Management Market

Handheld electronics such as PDAs, GPS receivers, games, and medical devices integrate a wide variety of logic, memory, and analog functions into a small battery powered unit. Efficiently providing power to all of the mixed signal components in such devices is a challenging proposition. A given product may have a wide number of voltage domains from 1.8V up to 40V. The core system processor may be a 1.8V or 3.3V device, the USB interface is running at 5V, LED and LED back lighting may require up to 40V supplies.

Power Sequencing

Power sequencing turns on the various voltage regulators in the correct order for power on, reset, sleep-modes, and power off states. Some voltages may require soft turn on where the voltage ramps to a requested voltage at a pre-programmed rate. This power sequencing requires digital timers and analog voltage sensing to control the sequencing and to detect over-voltage and fault conditions.

Regulator Topology Options

The power regulation topology options include linear regulators, switching regulators and low drop out (LDO) regulators. Buck regulators are used to reduce a high battery voltage down to 3.3V or 1.8V to power digital and low-voltage analog circuitry. Boost regulators are used to increase the battery voltage to provide higher voltages from 6V to 40V to such features as LED-based display
back lighting where a string of 10 LEDs can require voltages from 36 to 40V. A portable system can easily require 5 to 8 different regulators and the cost of the regulators and required support circuitry along with wasted PCB space can quickly add expense to a product.

Rechargeable Battery Management

Many portable systems contain rechargeable batteries and the power management solution has the responsibility of safely and quickly recharging the battery, monitoring of the battery’s capacity, and switching power from the battery to an external supply when connected to USB or an external transformer.

Power Management Building Blocks

Integrating the multiple power regulation components into a Triad Semiconductor via configurable array (VCA) saves on board area, component cost and manufacturing cost. Triad’s high voltage VCAs have an extensive set of mixed signal IP optimized for creating integrated power management controllers. The integrated controller saves cost and enables precise control of power sequencing, reset control, sleep-mode control, and brown-out sequencing. Triad’s power management building blocks include:

Power Management +Plus Triad VCA ASIC

Consider a typical portable application containing a microprocessor, back-lit LCD, audio, and capacitive button interfaces with the unit being powered by a lithium ion battery that is rechargeable via USB or an external power connection. This type of system has the following power management needs:

• 4.2 to 3.3V Regulation
• 4.2 to 3.3V Sleep-mode LDO Regulation
• 4.2 to 1.8V Regulation
• 5V to 4.2 Lithium-ion Battery Charging
• Battery Fuel Gauge
• Brown-Out Detector
• 36V Boost Regulator for LED-based LCD back-lighting
• Coordinated Power Sequencing for the individual Regulators

All of these functions can be integrated onto a Triad VCA. Triad’s high-voltage power management optimized VCA-2 platform is ideal for this type of application. The VCA-2 contains the following resources:

Digital Resources 9,000 Logic Gates 12 64×16 SRAM (12Kbits total SRAM) 1Kx8 EEPROM Supports multiple power regions from 2.6V to 50V Analog Resources 6 High Voltage General-Purpose Analog Tiles Each Tile has 2 op-amps plus arrays of: Capacitors, Resistors, Switches, Transistors 4 General-Purpose Analog Tiles Each Tile has 2 op-amps plus arrays of: Capacitors, Resistors, Switches, Transistors 1 High Voltage Reference Tile Boost-strapping band-gap to regulate high voltage down to 3.3V to start the power sequencing of the array 6 High Voltage Power Management Tiles 1 Reference Tile containing: Band-gap, 2 op-amps, Transistor Array for supplying bias currents 2 Wideband Amplifiers 2 Low Noise Amplifiers Analog to Digital Converter

Figure 2 - VCA-2 High Voltage Platform

The VCA-2 building blocks also enable the integration of non-power management features such as:

• Touch Screen Controller
• Capacitive Touch Button Interface
• Audio I2S Receiver
• Audio Class D Amplifier
• Audio H-Bridge
• General-Purpose Analog to Digital Converter

These functions can be combined into a single cost effect solution as shown in the ASIC block diagram in Figure 3.

Figure 3 – Power Management +Plus ASIC on Triad VCA-2

Smart Sensor Market

Smart Sensor is an umbrella term used to describe the addition of local intelligence to transducer information.

In the past, hooking up a transducer required dedicated point-to-point routing. The host processor needed to contain all of the information about the transducer before working with a sensor. A smart sensor contains interfaces to the transducer, analog processing, non-volatile memory that stores ‘datasheet’ information about the sensor, digital processing, and analog/digital communication links.

The smart sensor concept has been expressed in the family of IEEE1451 standards. These standards add Transducer Electronic Data Sheet (TEDS) information to the local sensor so that it can identify itself to the sensor network and support a plug-and-play approach to sensor integration. When a smart sensor is plugged into an acquisition network, the sensor identifies itself to the network, states what types of information will be reported, the engineering units used to report the data, manufacturer’s identification information, and extended manufacturer/user data.

Developers of smart sensor solutions are looking for these plug and play benefits while keeping transducer cost low and minimize power consumption.

Manufacturers are looking for:

Plug-and-Play - smart sensors enable easy system integration
Integration – reduce size and weight to support portable applications
Power Savings – required for portable applications
Sensor > to > Information

Transducer > Analog Interface > Data Converter > DSP > Non-volatile > Digital Communications Link

Triad VCA Building Blocks for Smart Sensor Applications

IEEE1451.4 Smart Sensor Triad VCA ASIC

Utilizing the VCA-4 platform, an IEEE1451.4 compatible Smart Sensor ASIC can be realized as shown in Figure 2 below. This ASIC provides the following features:

• Multi-Channel Analog Inputs
• Programmable Gain Amplifiers – Digitally Programmable Gain
• Low-Noise Input Amplifiers
• Single-Ended and Differential Inputs
• Analog Multiplexing
• Dual 10-bit DACs useful for external biasing or bridge excitation
• 16-bit Differential Sigma-Delta Analog to Digital Converter
• Digital Decimation and FIR Filter
• Integrated Single Cycle 8051 Microprocessor
  • RAM 3.75KB
  • EEPROM 8KB
  • Debug Interface
  • UART
  • Watchdog
• 32KHz PLL capable of generating a master clock from 32KHz to 2MHz – ideal for low-power sleep modes followed by high-speed processing and back to sleep
• UART off-chip Communication Link

This example implementation of a Smart Sensor Interface on the VCA-4 array provides high precision, low power analog processing, 16-bit analog to digital conversion, and a flexible 8051 integrated microprocessor subsystem to effectively transform raw transducer signals into useful system information. The transducer may provide raw temperature samples but the system is only interested in knowing when the temperature has gone above TEMP_MAX or below TEMP_MIN. Instead of sending the raw sensor data upstream to a central processor to manage, the local smart sensor processor reads temperature data, averages the data, and compares the results to the programmable TEMP_MAX and TEMP_MIN trigger levels. When the trigger levels are exceeded, the smart sensor sends a report to a networked central processor informing the processor that a particular sensor in the network has tripped a temperature alarm.

Non-Volatile Memory Uses in a Smart Sensor ASIC

• Reprogrammable Microcontroller
• Modify the 8051 program to accept data from different sensors enabling the ASIC to serve in more applications
• Extend the functionality of the Smart Sensor in the field via a boot-loader update of the program code over the UART serial link
• Calibration Data
• Temperature Compensation of Transducer Data
• Linearize Sensor Data
• Transducer Electronic Datasheet
  • Manufacturer ID
  • Sensor Serial Number
  • Sensor Type
  • Sensor Version
  • Amplifier Gain Settings
  • Analog and Digital Signal Path Settings
  • Sensor Data Format – Express results in engineering units
  • User defined data

Bioelectric amplifiers are used in EEG, ECG, and EMG applications like those shown Figure 1. These systems are used to measure electrical signals from the brain (EEG), heart (ECG/EKG), and muscles in general (EMG). A typical system can have from 1 to 256 sensor channels. The electrodes detect small electrical signals which require large amounts of gain and filtering to extract the information in the presence large common mode noise.

Many EEG/ECG/EMG systems are implemented as ‘boxes’ containing discrete analog circuitry to amplify and filter each sensor channel. Systems can have up to 256 channels and manufacturers are looking for:

• Integration - reduce size and weight to support portable applications
• Cost Reduction – reduce overall cost per electrode channel to support systems with up to 256 channels
• Power Savings – required for portable applications

Triad has ASIC building blocks, domain expertise in bioelectric amplifier circuit design, and existing VCA platforms optimized for the bioelectric amplifier marketplace.

Triad VCA Building Blocks for Bioelectric Amplifier Applications

4-Channel Bioelectric Amplifier Triad VCA ASIC

Utilizing the VCA-4 platform a 4-channel bioelectric amplifier can be realized as shown in Figure 2 below. This ASIC provides the following features:

• 4-channel Bioelectric Sensor Data Acquisition
• Low-Noise Input Stage: 2uVp-p input referred noise
• Input Stage Gain: 30dB
• Digitally Programmable Gain Stage: -5dB to +30dB
• Each channels gain independently settable via SPI commands
• 16-bit Sigma Delta Fully Differential Analog to Digital Converter
• Digital Decimation Filter & Stream Combiner with Serial Output
• SPI Control Interface (optionally IIC or UART)
• Package: 40-lead QFN, 6mm x 6mm

Notes:

1. Sampling frequency is adjustable by changing the ASIC master clock and/or through SPI control to change the clock generator divider ratio.
2. LPF Anti-aliasing filter cutoff frequency may be changed by changing the ASIC master clock or via SPI control. Additionally, alternative filter topologies can be implemented by schematic-only circuit changes which will require only a single mask fabrication change to the ASIC.

Migrating your mixed signal design to a Triad VCA means:

• Reduced cost
• Lower power
• Better integration
• Improved reliability
• IP Protection

If you thought that you could not afford a mixed signal ASIC then please consider the Triad advantage:

• Industry’s lowest NRE for mixed signal ASICs
• Accelerated development cycle (no full-custom layout needed)
• Fabrication time of 4 weeks
• Triad supports a wide range of conversion engagement models including complete turn-key design

FPGAs are a very good way to prototype a digital design.

Triad Semiconductor is a fabless supplier of via-configurable array (VCA) mixed signal ASICs. Triad VCAs combine silicon-proven analog and digital circuits onto a single semiconductor die.

The mixed signal resources of a VCA are overlaid with a global routing fabric. Wafers containing VCA die are then partially processed and staged at the foundry where they await customization.

A customer’s mixed signal design is configured onto a VCA platform by a single ASIC fabrication mask layer. As the name implies, via-configurable arrays utilize a single via layer mask to interconnect and configure resources throughout the VCA.

Users create VCA designs using industry standard design tools such as HDL/Schematic entry, simulation, and digital synthesis. Triad’s design flow supports any number of EDA tools that are capable of outputting digital gate-level netlists and SPICE-compatible analog netlists.

Triad’s via-only mixed-signal aware place and route software takes as input the user’s mixed signal netlist and outputs a via pattern when fabricated against staged VCA wafers results in an ASIC customized to deliver the functionality of the designer’s circuit.

Reduce cost

FPGAs are expensive devices… By migrating the entire design to a VCA mixed signal ASIC, both the FPGA and external components are all combined on the same die and inside the same package. This level of integration greatly reduces the required silicon area, removes package pins and results in significant system BOM cost savings.

Many mixed signal designs contain an FPGA plus analog components such as Op-Amps, analog to digital converters (ADC), digital to analog converters (DAC), and discrete resistors, capacitors, switches, and transistors. In addition to high unit cost of the FPGA, the bill of material (BOM) cost for the analog components can also be quite expensive.

While converting the FPGA to an all digital ASIC may seem like a good way to reduce system cost it can be of limited value in a mixed signal design. Yes, the silicon for a digital ASIC will be smaller than the FPGA silicon but there are more components to the system cost. If the FPGA is simply replaced with an ASIC, then all the I/O required to interface to the external analog components is still needed. If the design contains ADCs and DACs then dozens of pins will be required to connect these components to the digital-only ASIC. These wide buses on the ASIC and external parts increase the package cost for each part and the overall system BOM cost.

Configuration memories add cost… Many popular FPGAs store their configuration bit streams in expensive external configuration memories. Converting the design into a Triad VCA eliminates the area and expense of these configuration memories.

Improve Integration

Size does matter… For many space constrained applications integration of the mixed signal design into a chip-sized solution is the only option. VCA technology allows designers to integrate a rich set of analog and digital resources into space saving single integrated solutions.

An FPGA plus external mixed signal components often results in a lot of area consumed on a printed circuit board (PCB). Saving money by integration is important. Equally important for many applications is the need to fit a design into a smaller physical space. Absorbing the FPGA ADCs, DACs, resistors, capacitor, op-amps, voltage regulators, non-volatile memory (NVM), and transistors into the mixed signal VCA can reduce a PCB module into a small light weight single chip solution.

Higher Performance

Smaller, faster, cheaper… Via-configurable ASICs provide improved performance over PCB solutions implemented as an FPGA plus discrete analog components.

The ASIC-like architecture of a VCA is faster and less noisy than an FPGA solution. Additionally, VCA analog design techniques allow for the creation of high precision, low-noise analog and mixed signal functions that don’t require factory calibration or trimming. These same functions implemented as discrete analog functions on a PCB often require expensive precision components and time consuming and expensive factory calibration processes.

Just what is an FPGA gate anyway?… FPGA marketing material always talks about “system gates” as some sort of resource that enables FPGAs to talk about 100K or one million “system gate” gate counts. In practice, VCA ASIC designers find that an FPGA design that required 100K to 200K FPGA ‘gates’ may require as little as 10,000 VCA ASIC gates. FPGA “system gates” attempt to credit the FPGA with some equivalent gate count based on the amount of embedded memory within the FPGA. In fact, FPGA vendors have in recent years done a pretty good job in encouraging users to utilize these memory resources for FIFO and other processing units. When the designer has looked to migrate a memory-rich FPGA design to an ASIC design they often found that extensive use of memories made the standard-cell based implementation of the ASIC larger than would have been anticipated.

Triad VCA ASICs contain logic tiles populated with via configurable ASIC gates so that Triad gate counts are much more like traditional 2-input NAND gate ASIC gate counts. Plus, VCA logic tiles contain integrated distributed memories in single-port and dual-port configurations which absorb FPGA memory resources without introducing routing blockages. The distributed memory in the logic tiles is in fact quite porous in the global routing fabric layers of the device. From a silicon area point of view the VCA distributed memory is effectively free since it is underneath the logic routing channels.

IP Protection

Stealing an FPGA design is too easy… Placing a mixed signal design into a via-configurable ASIC provides much stronger protection of the design IP and prevents cloning.

FPGAs are programmed using bit streams stored in external configuration memories. These memories are completely insecure allowing anyone to intercept the FPGA bit stream as it goes between the memory and the FPGA. With the bit stream, the design can be reverse engineered or simply replicated.

FPGA designs are vulnerable to cloning. Reverse engineering an FPGA bit stream back to a working netlist requires a fair amount of engineering effort. More likely in some of today’s outsourced manufacturing environments it the risk of FPGA cloning. A contract manufacturer may produce a given number of FPGA-based products for their customer and in addition to these legitimately manufactured products they may clone the FPGA and illegally produce extra units that the manufacturer then directly sells in the market place.

Lower Power

FPGAs are power hungry… Power consumption can be reduced more than 10x by converting an FPGA design to a via-configurable ASIC.

The massive amounts of active switching and high current drivers within an FPGA make such devices terribly power hungry. Via configured ASICs on the other hand use low resistance metal and via connections which greatly reduce capacitances and switch currents and hence power consumption.

External busses burn power… Many mixed signal designs interface FPGAs to high speed ADCs and DACs with wide, fast switching parallel busses. The I/O drivers in the FPGA and the data converters consume large amounts of current. By integrating the ADCs and DACs with the digital logic on the same VCA ASIC, the high current I/O is replaced with much lower power internal busses.

Improved Reliability

Make things simple to make them more reliable… VCA ASICs contain fully-characterized, silicon-proven mixed signal resources that are delivered as factory-tested, packaged parts that significantly reduce manufacturing complexity and improve product reliability.

More components mean more problems… A PCB design consisting of an FPGA plus a wide variety of external mixed signal components is a much more complicated manufacturing process than placing a single via configurable device onto a PCB. The handling, assembly, and soldering of all the parts on a complex mixed signal PCB is often a major source of reduced product reliability. Reduced reliability results in increased factory test cost, scrap cost, rises in product failure rates, and increased warranty service costs.

VCA Mixed Signal Resources

Triad’s via configurable array (VCA) platforms contain a rich assortment of essential mixed signal design elements. The silicon-proven resources can be combined to develop single chip solutions for a wide variety of applications.

VCA Mixed Signal IP List

Engagement Models

Triad is here to help… Triad’s engineering team is experienced in ASIC, FPGA, and VCA design and they are ready to help quickly and efficiently convert FPGA plus discrete analog designs to a single chip VCA solution.

Turn-key design… Many customers opt to let Triad’s VCA development team handle the entire job of converting an existing PCB design to a VCA ASIC. For a turn-key migration, Triad FAEs and engineers work with the customer to analyze the discrete design, develop a specification for the VCA ASIC and perform all of the engineering necessary to convert the design to a VCA.

For customers with working FPGA designs and moderate analog design complexity, Triad can convert the design into a VCA format in as little as 8 weeks. Following design completion, Triad and the customer undergo a joint design review and submit or tape-out the design to the foundry for single mask fabrication. Prototypes are available from the foundry 4 weeks after tape-out.

Customer-driven design… Customers can create a complete mixed signal VCA design using their own tools along with Triad’s mixed signal design kit (MDK). The Triad MDK contains VCA primitive datasheets, SPICE-compatible macro models of analog components, digital simulation libraries, and digital synthesis libraries. Customers perform HDL/Schematic capture for the analog and digital portions of the design, perform simulation, and digital synthesis. The synthesized gate-level netlist of the digital design along with the SPICE netlist for the analog section is submitted to Triad. Triad and the customer perform a joint preliminary design review and Triad provides the back and place and route services using VCA-specific via-only place and route software. After place and route, Triad and the customer undergo a final joint design review and submit or tape-out the design to the foundry for single mask fabrication. Prototypes are available from the foundry 4 weeks after tape-out.

Cooperative Design… Triad engineering is available to work with the customer to successfully migrate an FPGA plus discrete analog design to a VCA. The customer may have expertise in digital design but may be lacking in analog design capacity or vice versa. Triad engineering is available to provide analog digital or mixed signal design services as needed to migrate the design to a VCA.

Triad is here to help designer successfully and cost effectively convert designs to a VCA solution.

Sigma delta A/D converters (ΣΔ-ADC) combine over sampling analog sigma delta modulators with digital decimation filters to achieve high precision and cost effective A/D conversion solutions. ΣΔ-ADCs are used to implement high-precision, low-power A/D converters for applications such as sensor interfaces and audio processing. Until recently a delta sigma solution needing mixed signal circuits has required full-custom ASIC design. New design techniques incorporating via-configurable array (VCA) technology allow mixed signal IP such as ΣΔ converters to be created and reused as soft-IP.

Analog to Digital Conversion Theory

Analog to digital conversion (ADC) is the process of sampling a continuous analog signal and converting the signal into a quantitized representation of the signal in the digital domain. Many different ADC architectures are available to convert analog signals into digital representations. The conventional ADC process transforms an analog input signal x(t) into a sequence of digital codes x(n) at a sampling rate of fS = 1/T, where T denotes the sampling interval. The sampling function is equivalent to modulating the input signal by a set of carrier signals having frequencies of 0, fS, 2fS, 3fS,…, see Figure 1. The sampled signal may be expressed as the summation of the original signal component and the signal?s frequency modulated by integer multiples of the sampling frequency. Therefore, any signal components about the Nyquist frequency in the input signal cannot be properly sampled and such signals in fact will get ?folded? into the base-band signal creating artifacts in the sampled signal which were not present in the original input signal. This non-linear ?folding? or signal distortion is referred to as aliasing. Anti-aliasing filters are therefore required to prevent or reduce these aliasing artifacts. Many A/D converters such as successive approximation register (SAR) and flash converters operate at the Nyquist rate (fN). These converters typically sample the analog signal at a sample frequency (fS) approximately twice the maximum frequency of the input signal. A Nyquist rate ADC converts the analog signal into an n-bit representation at every Nyquist sample time. Since the Nyquist rate may only be approximately 2x the frequency of the sample pass band of interest a high-performance low pass filter (anti-aliasing filter) is required to limit the maximum frequency components input to the A/D converter.

Figure 1 – Analog and Sampled Signals with Aliasing

Sigma delta A/D converters do not instantly digitize the incoming analog signal into a digital sample of n-bit precision at the Nyquist rate. Instead, a sigma delta ADC over samples the analog signal by an over sample ratio of (N) resulting in f_N << f_S (over sample rates of 16, 32, 64, 128 are common). The over sampling A/D conversion is performed at a lower precision (coarser quantization). In fact, many ΣΔ-ADC are effectively a 1-bit A/D. As shown in Figure 2, the output of the modulator or 1-bit A/D is a bit stream with the one?s density of the stream proportional to the magnitude of the sine-wave input. This 1-bit A/D stream that is generated at N*fS (Over Sampling Rate * NyQuist Rate) can be digitally filtered and decimated back down to a Nyquist rate of n-bit precision samples.

Figure 2 – ΣΔ modulator output representing sine-wave input

The 1-bit A/D stream is digitally filtered to obtain an n-bit representation of the analog input. In simplified terms the 1-bit A/D stream is accumulated over (N) sampling cycles and divided by (N). This yields a decimated value which is the average value of bit stream from the modulator as shown in Figure 3.

Figure 3 – ΣΔ A/D stream accumulated and decimated to represent an n-bit value of the input

In addition to anti-aliasing, a Nyquist rate ADC also requires a precise sample and hold analog circuit. The circuit holds continuous amplitude, discrete time samples of the analog waveform stable while the converter performs the quantization. The sample and hold output is compared to a set of reference levels within the ADC. The quality and precision of these reference levels is a limiting factor for high resolution A/D converters. For example, a 16-bit Nyquist rate ADC requires 2¹⁶ ? 1 (65535 different reference levels). A typical converter may span a 2V input range. The spacing between any two reference levels is only 30 _μV. This type of matching is difficult to achieve on an integrated circuit without the use of expensive and complicated trimming techniques.

One of the major advantages of a ΣΔ-ADC over a conventional parallel or Nyquist ADC is the relaxation of the requirements for the anti-aliasing filter. As mentioned above, the requirements of an anti-aliasing filter for a Nyquist rate ADC require a sharp transition from the pass band (f_B) to stop band (f_N) as shown in . The anti-aliasing filter for a conventional ADC needs to be flat through the pass band and attenuate signals above the stop band by an attenuation factor greater than the dynamic range of the ADC.

Figure 4 – Transition band for Nyquist and over sampled converters

An over sampling A/D converter moves the sampling frequency (fS) much farther away from the Nyquist frequency than a Nyquist rate converter by a factor of (N). Since the complexity of an anti-aliasing filter is highly proportional to the ratio of the width of the transition band to the width of the pass band, over sampled converters require far simpler anti-aliasing filters than Nyquist rate converters with similar performance. What may have been a complex filter requiring significant component matching for a Nyquist rate converter may be replaced by a simple R-C filter in an over sampled converter.

Sigma Delta A/D Implementation

A ΣΔ A/D converter is a mixed signal design consisting of an analog ΣΔ modulator followed by a digital filter as shown in Figure 5. This implementation shown here is a fully differential second order modulator followed by a Sinc3 decimation filter.

Figure 5 – High-level view of delta-sigma modulator

Delta Sigma Modulator

For analysis purposes a second order delta sigma modulator can be represented by the block diagram of Figure 6.

Figure 6 Block diagram of a second order ΣΔ modulator

The first summation and function H₁(z) represents the first integrator, the second summation and function H₂(z) represents the second integrator, and the third summer represents the comparator, where QN(z) is the quantization noise generated by the comparator. Note the one-bit DAC in the feedback loop is considered ideal and is not shown in Figure 6. That is to say when the output of the modulator is a logic one, the output of the DAC is a positive reference voltage while the opposite occurs when the output of the modulator is a logic zero. Analysis of the block diagram yields the transfer function for the modulator as shown in Equation 1.

IN(z) is the input signal, H1(z) and H2(z) are the integrator transfer functions, QN(z) is the quantization noise generated by the comparator, and OUT(z) is the modulator output. The block diagram shows the summers in the integrators output the difference between the output signal and the input to each integrator (Δ), while the H(z) functions are chosen so they sum (accumulate) these differences (Σ). This functionality permits the average input to match the average output. For example, given a sinusoidal input whose peak to peak amplitude is near the maximum allowable peak to peak amplitude of the modulator; when the input is at its maximum positive peak the output of the modulator should be nearly all logic ones. As the signal passes through the mid-point of the wave the modulator output should be an even mix of logic ones and zeroes. Finally, as the sinusoidal input is at its minimum peak the modulator output should be nearly all logic zeroes.

The schematic for a second order ΣΔ modulator is shown in Figure 7 and is constructed of two switched capacitor integrators, a clocked comparator, a 1-bit digital to analog converter and a non-overlapping clock generator. The schematic is targeted to primitives on a via configurable array (VCA) platform developed by Triad Semiconductor. VCA platforms contain pre-diffused analog and digital resources that are interconnected by placing vias in a global routing fabric.

Figure 7 – Differential 2nd order ΣΔ modulator implemented with VCA primitives

As mentioned above, the H(z) transfer functions must be selected so the average input equals the average output. To accomplish this, the first integrator was chosen to be a delay free, parasitic insensitive integrator whose half circuit transfer function is shown in Equation 2.

In this implementation C₁ is 4 pF and C₂ is 2 pF. This gives a gain of one-half. The second integrator is a parasitic insensitive integrator whose transfer function is shown in Equation 3.

As with the first integrator, C₁ is 4 pF and C2 is 2 pF, thus giving a gain of one-half. The gains for the integrators are set in this fashion to ensure the integrators do not saturate. Also to help avoid saturation, the amplifiers used in the integrators have rail-to-rail output swing capability. The clocked comparator acts as the 1-bit quantizer and consists of an amplifier whose output is connected to the D input of a flip flop. The output of the flip flop (Q) is a logic one when the voltage between the non-inverting input and the inverting input (also, non-inverting output and inverting output of the second integrator respectively) is positive and is a logic zero when the voltage is negative. The output of the comparator (also the output of the modulator) controls the one-bit DAC in the feedback path. The one-bit DAC consists of transmission gates that determine the polarity of a reference voltage to be summed with the inputs of the integrators. For the first integrator, when the output of the modulator is a logic one, the non-inverting input is summed with the negative reference voltage. Conversely, the inverting input of the first integrator is summed with the positive reference voltage when the modulator output is a logic one. The polarity of the input and the polarity of the reference voltage do not match (i.e., the non-inverting input is summed with the inverting reference when the modulator output is a logic one) for the first integrator because its transfer function is inverting. This is required for the ΣΔ modulator to be stable. For the second integrator the polarity of the reference voltage matches the polarity of the input. Substitution of Equation 2 and Equation 3 into Equation 1 results in Equation 4.

Equation 4 reveals the input signal is merely delayed whereas the quantization noise is moved to higher frequencies by a second-order differential function. The shifting of quantization noise to higher frequencies is why ΣΔ modulators are also referred to as noise shaping modulators. Provided the frequency of the input signal is low relative to the sample rate of the ΣΔ modulator, and a digital low pass filter is used, the quantization noise is greatly reduced. The quantization noise can be reduced further by increasing the order of the modulator at the expense of complexity and increased component count. Also, it has been shown for an analog to digital converter employing the second order modulator discussed here, the ideal signal to noise ratio for a sinusoid is given by Equation 5.

Here fsignal is the highest frequency of interest in the input signal and fsample is the sample rate (clock frequency for the ΣΔ modulator.) The sample frequency divided by the input signal frequency is known as the over sampling ratio. Inspection of Equation 5 shows with every doubling of the over sampling ratio the ideal signal to noise ratio increases by 15 dB.

Sigma Delta Modulator Performance

The performance of the ΣΔ modulator can be quantified by collecting output data using a sinusoidal input source over several seconds. It is necessary to collect data for a long period of time (3 to 5 seconds) to attain good low frequency resolution. Also it should be noted, the signal source must have an SNR greater than the resolution of the A/D. This data can then be post processed with an FFT to view the signal in the frequency domain as shown in Figure 8. In this case the input signal frequency is 100 Hz and the ΣΔ modulator sample rate is 500 kS/s. Notice the noise floor is more than 100 dB below the maximum amplitude of the input signal (with the exception of some harmonics due to the signal generator) up to approximately 3 kHz. In other words, this ΣΔ modulator is suitable for realization of a 16 bit A/D for an over-sampling ratio of 500/3 = 167 which approximately concurs with Equation 5.

Figure 8 – 2nd order ΣΔ modulator spectral plot for sinusoidal input.

Digital Filtering

The over-sampled output of the ΣΔ modulator is processed by the digital filter shown in Figure 9. The decimation filter consists of a 3 stage accumulator that serves as a Sinc3 filter followed by a 3 stage differentiator decimator circuit.

Figure 9 – Sinc3 digital decimation filter

The DSM_IN 1-bit input stream is accumulated and decimated to create a 16-bit data word that is output at the ADC Nyquist word rate. The filter is implemented as Verilog RTL code as shown below.

Video color space converters are mixed signal circuits that convert video signals from one color space such as RGB to another color space such as YCrCb utilizing high speed digital logic, ADCs, and DACs.

This application note provides a brief overview of color space conversion and the development of a single chip mixed signal ASIC color space converter implemented on a Triad Semiconductor VCA-6160 platform.

2 Color Space Introduction

Many video applications require converting video and image content from one color space to another. Images and motion images (video) have utilized a wide variety of color spaces including: RGB, YCrCb, HSI, and other formats to represent the colors within the image. Each of these color space representations has its own set of advantages and disadvantages. For example, RGB is often used for the most demanding applications where ultimate color fidelity must be maintained. Any given color that the human eye can see may be represented by a combination of the primary colors (Red -R, Blue -B, and Green -G). The human eye doesn’t actually see equally well in the different color bands with our human-vision system optimized for the red, green bands but not quite as sensitive to changes in blues. Scientist and engineers looking for was to reduce the bandwidth and/or bit rate of a video system have created other color spaces (and sampling spaces) that reduce the amount of blue information in a system while maintaining a subjectively high picture quality. Furthermore, human vision is more highly tuned to changes in brightness (black and white or gray-scale changes) than it is to changes in hue (changes from one color or another with the same brightness). Therefore, many video systems sub-sample the color information (chrominance) while transmitting the black and white (luminance) in full resolution. This sub-sampling is often applied to luminance-chrominance color space systems such as YCrCb where Y represents the luminance information and Cr and Cb are color difference signals that represent the chrominance information. In these systems all of the Y samples are used but every other color sample is dropped. These systems are referred to as 4:2:2 sampling. The 4:2:2 nomenclature signifies that for every 4 Y samples only 2 Cr and 2 Cb samples are saved. Owing to the bandwidth saving benefits of these different image formats different video equipment will adopt different color space encodings. Interoperability between such equipment often requires a device to convert the output of one video device in a given color space to the color space needed as input for the down stream device. Some examples of color space conversion are the converting of the RGB video output from a computer VGA card to YCrCb input on a TV monitor. The opposite conversion path is also common where a video device such as a DVD player outputs YCrCb and the video needs to be converted to RGB to drive a monitor.

3 Color Space Conversion Math

Color space conversion is a matrix operation which is uniquely defined for conversion from one color space to another. For example, YCrCb data may be derived from RGB data by the following transformation:

[ Y  ]		[ 0.299  0.587  0.114 ] [ R ]
[ Cr ]	=	[ 0.596 -0.275 -0.321 ] [ G ]
[ Cb ]		[ 0.212 -0.523  0.311 ] [ B ]

These conversions are performed as digital multiplication and addition utilizing fixed-point multipliers and summation circuits as shown below:

Figure 1 – RGB to YCrCb Digital Matrix Math

Depending on the technology used to implement the digital matrix math, different clock rates may be supported and differing amounts of pipelining may be required to obtain the desired sample rate through the matrix operation.

While this matrix math function is relatively straight-forward a real color space conversion system requires an analog interface to accept the incoming analog signals in RGB-space and to output the analog YCrCb signals. Based-band video signals have analog bandwidths from a few megahertz for low resolution imaging systems upwards of 80 MHz for HDTV resolution systems. High fidelity video systems require from 6 to 10 bits of resolution per baseband analog channel. Therefore, an RGB system needs digital to analog (DAC) and analog to digital (ADC) components with 6 to 10-bits of resolution and sampling rates in the tens of MHz.

A complete color space converter system needs not only high-speed digital logic to perform the matrix math operation but high-speed ADC and high-speed DAC functions to accept analog RGB and output analog YCrCb. A complete mixed signal color space converter system on a chip (SOC) might look as follows:

Figure 2 – RGB to YCrCb Mixed Signal ASIC on a Triad VCA Platform

This application specific integrated circuit (ASIC) implementation of the color space converter requires digital logic, 3 10-bit, 30 MSPS ADCs, and 3 10-bit, 30 MSPS DACs, plus a PLL and clock driver circuitry. While the digital portion of the color space converter can be implemented in an FPGA without a major engineering expense, such a solution will require discrete ADCs and DACs driving up the system parts count, bill-of-materials (BOM) cost, manufacturing cost, power consumption, and will lower overall reliability of the system. Implementing the color space converter as a mixed signal full-custom ASIC is an option but this option is viable for only the highest volume products and requires significant engineering and fabrication expenditures. Full custom ASIC design is expensive and time consuming and often requires multiple re-spins at the foundry to correct problems associated with the integration of analog and digital elements.

Modification and enhancements to the above design might include the addition of more pipeline stages for higher speed operation, the ability to change the coefficients on in the matrix section to support conversions to other color spaces. Allow for YCrCb to RGB conversion and RGB to YUV conversion. A further enhancement that is possible with the mixed signal resources within a Triad VCA is the inclusion of an NTSC or PAL encoder that would allow for RGB to NTSC or YCrCb to NTSC/PAL conversion.

4 Low-Cost, Low-Risk Mixed Signal ASIC Development

An alternative implementation to the FPGA / discrete and full-custom ASIC options is the use of a mixed signal via configurable array (VCA). The VCA combines the positive attributes of both the FPGA and full-custom devices. A VCA is a mixed signal structured ASIC device that combines silicon-proven analog and digital resources onto a single semiconductor die. These mixed signal resources are then overlaid with a global routing fabric. The VCA platform is then partially processed at the foundry up through some of the metal routing layers. Wafers containing partially processed VCA die are then staged at the foundry awaiting customization. VCA platforms are configured by a single mask layer that defines vias between the globally defined routing fabric. Vias make connections between different metal routing layers thereby interconnecting and configuring the various digital and analog resources within a platform.

VCA platforms contain a wide range of useful mixed signal resources including:

• High Speed Analog to Digital Converters
• High Speed Digital to Analog Converters
• PLLs
• Analog Tiles Containing
• Op-Amps (Low Power, Low Noise, Wide Band, Fully Differential)
• Capacitor Arrays
• Resistor Arrays
• Switch Arrays (pass gates, SPST, SPDT)
• Transistor Arrays
• Temperature Sensors, Band-Gaps, Voltage References
• Logic Tiles containing from 4,000 to 200K ASIC gates
• Distributed RAM (single port and dual port)
• Non-Volatile Memory
• ROM
• Configurable Digital I/O
• Configurable Analog I/O
• Isolated Analog and Digital Power
• Shielded analog and digital routing

The complete RGB to YCrCb mixed signal color space converter circuitry can be implemented on a single Triad VCA-6160 platform. The VCA-6160 platform is shown below and contains:

Digital Resources

• 160K ASIC Gates
• 216Kb Dual-Port RAM (216 1Kbit RAMs)
• 4 200 MHz PLL
• 160 Configurable Digital I/O
• 3.3V Digital Operating Voltage

Analog Resources

• 10-bit, 30-MSPS Current Steering DACs
• 3 10-bit, 30-MSPS Pipelined ADCs
• 24 Fully Differential (FD) Op-Amp Tiles (48 FD Op-Amps)
• 12 General Purpose (GP) Op-Amp Tiles (24 GP OTAs)
• 4 10-bit, 1-MSPS R2R DACs
• 2 8-bit, 1-MSPS ADC
• Temperature Sensor
• Band-Gap, Voltage Reference Network

Figure 3 – Triad VCA-6160 Platform

5 Design Approach

The digital portion of the color space converter algorithm is created using Verilog to describe the RGB to YCrCb matrix math operations. This portion of the design is then simulated using Mentor Modelsim to verify the correct functionality of the digital portion of the design. The analog portion of the design is captures in Mentor Design Architect using analog primitives from Triad’s mixed signal design kit (MDK). The resultant analog design of ADCs and DACs is simulated using a Spice simulator coupled with Triad Spice macro-models that are also provided in the MDK. The next step in creating the design database is to synthesize the digital portion of the design using any of a number of industry-standard synthesis programs. This process maps the HDL RTL description of the design into Triad digital primitives contained within a structural Verilog netlist. The analog portion of the design which is represented by a Spice netlist is processed using Triad software to convert the Spice netlist into a structural Verilog netlist representing the analog portion of the design. The analog and digital Verilog netlists are then merged into a single mixed signal structural Verilog netlist. This netlist represents the instantiation and interconnection of all of the digital and analog resources used within the design. The mixed signal netlist is then provided as input to ViaPath(TM) a via only place and route program which automatically places and routes both the digital and analog portions of the design. The output of the ViaPath(TM) router is a single via layer describing the vias needed to configure and interconnect the entire VCA-6160 platform. This single mask layer is then sent to the foundry to be processed against staged VCA-6160 wafers to create a mixed signal ASIC color space converter IC.

Figure 4 – Triad VCA Design Flow

6 Summary

Video and imaging applications are by nature composed of high speed analog and digital circuits. Many such applications have been prototyped and even taken into low volume production using FPGAs and discrete analog devices. As cost, power, and performance pressures come to bare on such products converting the design to a single-chip, low cost, low power, high performance mixed signal ASIC is an obvious choice. An obvious choice except for the large development schedule, high NRE, and major risk associated with a typical full-custom mixed signal ASIC development. Using Triad’s VCA-6160 platform a designer can quickly, easily, with low risk, and low development cost create optimized.