Triad Semiconductor

Market: Utility, Meter Reading, SmartGrid

Target Platform: Mocha™-Family – ARM® Cortex™-M0 Configurable Arrays

Application: Complete Automatic Meter Reading SoC

The TM0X11 combines a high-performance ARM® Cortex™-M0 32-bit processor optimized for deterministic embedded applications with a precision data acquisition system to provide a complete automatic meter reading (AMR) solution on a single power monitoring SoC. The Cortex-M0 support 0.8 DMIPS / MHz and can operate at frequencies up to 40 MHz. The precision analog system on the TM0X11 supports multi-channel current and voltage measurements with 24-bit sigma-delta analog to digital converters.

Flexible – Via Configurable Architecture
The TM0X11 design is implemented on TRIAD’s Cortex-M0 mixed signal configurable array (Mocha-1). The Mocha-1 is a via configurable array (VCA) containing a highperformance hardened Cortex-M0 microprocessor subsystem and configurable analog and digital resources. The TM0X11 design can be modified and debilitative products created by a single, low-cost via-mask layer change with new prototypes available in 4 weeks after tape out.

 ARM Cortex-M0 32-bit Processor

The ARM Cortex-M0 is a highly optimized 32-bit processor targeting mixed-signal and SoC applications that sets new performance, power, and determinism standards for deeply embedded applications. 

• ARM Cortex-M0 32-Bit Core
  • Binary forwards compatible with Cortex-M3 and Cortex-M1
  • Dynamic Power for Dhrystone loop: 130 uW/MHz (1.8V, 25C)
  • Dynamic power half that of the Cortex-M3
  • 50MHz operation
  • 0.8 DMIPS/MHz 
• Hardware Multiplier 32 x 32 à 32 bits, single cycle
• Integrated system timer (SysTick) and corresponding exception
• AHB-Lite interface for instructions and data
• Low latency AHB (peripheral bus) access for external load / store operations
• Thumb-1 instruction set plus a subset of Thumb-2 instruction.
• Deterministic instruction timing
  • Fixed interrupt latency of 16 cycles
  • Support for hardware stacking and unstacking of a subset of registers on exception entry and return
  • Low overall ISR entry and exit latencies
  • Exception handlers can be written in C without the need for assembler stubs
  • Interruptible-load-store multipliers for low interrupt latency.
  • WFI / WFE instructions to enable low-power sleep modes.
• Interrupt Controller (NVIC)
  • Software control of each interrupt
    • 4-level priority configuration
    • Enable / disable
    • Pend and un-pend functionality
  • Support for both level-sensitive and edge sensitive interrupts
  • Dedicated non-maskable interrupt (NMI)
  • Closely coupled with processor core for efficient exception handling:
    • Support for late-arriving exceptions to avoid having to re-stack context
    • Support for tail-chaining to reduce interrupt latency by folding together exception exit unstacking and subsequent exception entry stacking to allow direct intro into the ISR
• CoreSight^TM Compliant debug solution
  • Low-pin count JTAG or Serial-Wire interface to the debugger
  • Debug Halt mode
  • Access to memory and memory mapped registers while the processor is running or halted
  • Debug access to processor registers while the processor is halted
  • Watchpoint comparators that allow data address and instruction address matching and masking functionality
  • Breakpoint comparators that allow instruction address matching
  • BKPT instruction to allow unlimited number of breakpoints to be set in RAM regions of code