Triad Semiconductor

Via-configurable array (VCA) technology enables the rapid development and low cost design of feature-rich mixed-signal ASICs that integrate sophisticated analog IP blocks without the pain and risk of full-custom design.

To IP or Not to IP

Although all real engineers would like to create all of their designs from scratch, that just is not practical in today’s fast-paced ASIC development world. The need to integrate intellectual property (IP) from third-party providers is the reality.

Engineers are also realizing that convergence is real in the ASIC world. More and more ICs are requiring the integration of digital and analog functions onto the same device. Today’s applications need digital processing coupled with analog to digital converters (ADC), digital to analog converters (DAC), PLLs, op-amps, analog filters, voltage regulators, and on and on. Even seemingly digital communication links such as USB and FireWire contain sophisticated mixed-signal physical interface (PHY) circuits. On the digital side, designers must develop or integrate communication links, microcontrollers, memory interfaces, DSP processing, and local control circuitry.

To add to the integration problem, there are not many ASIC designers that are equally well versed in both analog and digital design. Instead most are either 90% analog and 10% digital or 90% digital and 10% analog. Actually, for the digital engineers, many are 99% digital and 1% analog, but that’s a different article. (If you think you are a 50/50 or even a 60/40 designer then send me an e-mail - I would like hear from you).

The complexity of these varied development requirements coupled with time-to-market pressures force companies to consider integrating IP blocks from third-party suppliers. Advances in mixed-signal via-configurable array (VCA) technology are enabling analog soft-IP integration that emulates the rapid, efficient, and cost effective IP use found in all-digital FPGAs.

Digital IP - Difficult but Doable

When companies realize that they cannot develop all of the IP needed for an ASIC in a timely and cost effective manner, the search for third-party IP begins. In theory, digital IP has always been available in the form of GDSII layout blocks representing a particular function. Such blocks have constrained, or ‘hard,’ features–including aspect ratio, power and clock routing, internal timing, power consumption–and they are tied to exactly one process at one integrated chip (IC) foundry. With all of these fixed or hard parameters, this type of IP block has often been referred to as ‘hard IP,’ where ‘hard’ meant fixed parameters as well as hard to work with.

Digital IP sharing became widespread when designers advanced up from physical design and even schematic capture to the more interchangeable design format of a hardware description language (HDL). The adoption of Verilog and VHDL HDLs coupled with synthesis electronic design automation (EDA) tools enabled designers to express designs in a format independent of foundry, ASIC vendor library, and EDA toolset. Functions described in an HDL no longer had the fixed constraints of hard IP. An HDL IP block could be modified by synthesis to optimize its aspect ratio, timing, power, and routing resources and, most importantly, the IP was no longer tied to a particular process or foundry. The relaxation of constraints that HDL-based IP required led many to describe this new IP exchange format as ’soft IP.’

The widespread use of HDLs and soft IP makes interchange of digital IP technically feasible but integrating someone else’s IP can be a significant effort. Once a company decides to use third-party IP many different factors must be evaluated and many of them, as shown in , are not technical issues. Many companies find that a considerable amount of time and cost is associated with evaluating and integrating third-party IP.

Table 1 - Factors companies consider when integrating digital IP

The FPGA Guys - Easy to use Free IP for the Masses

There’s a dirty little saying in the EDA and IP business that goes something like ‘the best customer buys EDA tools and licenses IP and then goes out of business before ever using them.’ For the most part, the third-party IP business is setup like the EDA business, where vendors want to get all of their money on the front end. The exceptions to this approach are the FPGA companies that give away a lot of quality IP. Yes, the FPGA companies must pay for the development of their IP and pass the cost along to their customers as an increase in the silicon unit-price but since these costs are spread out across a large user base, the incremental costs are negligible. And, companies don’t pay for the IP until they are actually selling products and making money themselves. The FPGA approach focuses on removing the cost and integration barriers so that users can quickly get silicon to market and then the FPGA company makes money with the customer. FPGA vendor IP comes with a significant reduction in IP integration issues. The FPGA vendor provides consistent documentation, integration support, and a uniform development flow. By making IP easy to use and eliminating large up-front charges, FPGA products have captured a significant part of the IC market that was historically dominated by ASICs.

Analog IP Stumbling Blocks

Digital IP is a necessary part of IC development. And the FPGA IP distribution model really works. So, what is the state of analog IP? Simply put, analog IP is hard to use. Analog IP comes with all of the evaluation and integration issues associated with digital IP plus a set of issues unique to analog. Analog IP is provided as hard IP in the form of GDSII layout blocks. These blocks are fixed in size, tied to a particular foundry and process, and they are often difficult to integrate. Getting rid of noise problems from nearby circuits is often a problem due to the fixed layout of the circuits within a hard IP block. Integrating high performance analog IP with high speed digital logic on the same complementary metal-oxide-semiconductor (CMOS) die is a science and an art that, for even the best design teams, requires multiple fabrications at the foundry.

Soft IP for the Analog ASIC - Impossible yet True

What if designers could use analog IP the way they use digital IP from FPGA companies? What is needed is a framework and integration method that allows developers to easily integrate mixed-signal building blocks into complete designs. Digital IP sharing and FPGA use became pervasive as designers moved up in abstraction from physical or full-custom design. Sure, higher levels of design abstraction are slightly less efficient but companies have reaped such benefits from this approach that it is difficult to find many people doing full-custom digital design these days. If mixed-signal soft IP could be provided by an ASIC company free of charge, then companies could adopt a get-to-market-quickly approach without paying large up-front licensing fees and spending effort on third-party IP evaluation.

If a configurable approach could be brought to mixed-signal development, then analog designers could more easily reuse designs and share IP. Via-configurable array (VCA) technology incorporates silicon-proven analog and digital resources on a single semiconductor die. These resources are then covered with a global routing fabric that can be completely configured and interconnected with a single fabrication mask change, as shown in Figure 1.

Figure 1 - VCA global routing fabric configured by auto placing vias to interconnect resources

Maybe some analog designers reading this are thinking “every polygon and transistor must be hand-crafted to make an elegant design.” And, for the few cases where this is true, analog designers should stay with full-custom layout. For the vast majority of designers, however, having a set of silicon-proven configurable mixed-signal building blocks plus free mixed-signal IP would result in a real productivity improvement.

The History of Analog Arrays - Size Does Matter

In the past, configurable analog arrays consisted of either “fine-grain” or “coarse-grain” approaches. The fine-grain solutions consisted of a sea-of-transistors that could only be manually interconnected by customizing the metal and via layers of the device. This approach worked for very small analog-only designs but the routing complexity associated with this method prohibited this architecture from scaling to larger designs or designs that contained any appreciable amount of digital. The manual selection of transistors and routing also severely limited IP reuse in these architectures. The course-grain approaches consisted of large analog blocks that were configured as a limited number of macro functions such as low-pass filters or data converters. The parameters on the filters and converters could be adjusted but the large blocks could not be decomposed into smaller blocks to build other circuits. The course-grain solutions offered little flexibility and could not be used if the circuit did not match the platform macro resources.

Today’s Via-configurable Analog Arrays

Today’s configurable mixed-signal solutions, Via-configurable arrays, are built from “medium-grain” resources. Instead of being a sea-of-transistors or macro-function blocks, VCAs utilize tiles containing common analog resources that can be combined into a variety of circuits. VCA analog tiles contain operational amplifiers, buffers, and bias generators. In addition to these resources each analog tile contains arrays of capacitors, resistors, switches, transistors, and local logic, as shown in Figure 2.

VCAs are built from a variety of analog tiles optimized for single-ended, fully-differential, wide-band, lower-power, or high-voltage operation. These resources are the basic building blocks for a wide range of analog circuits such as: continuous time filters, switched capacitor filters, programmable gain stages, pulse width modulators, sigma delta modulators, analog to digital converters, and digital to analog converters. VCAs also contain high performance ADC, DAC, h-bridge, and power regulator tiles. Unlike traditional full-custom hard IP or the coarse-grained configurable IP blocks, these VCA resources are fully via-configurable, allowing them to be rearranged into other analog circuits as needed by the customer’s design using automated via-only place and route software.

Figure 2 - Mapping of an analog circuit to a via-configurable array

In addition to a fully configurable set of analog resources, VCA platforms contain digital tiles that combine logic and memory resources. These VCAs are capable of supporting high performance mixed-signal IP blocks and designs. Companies adopting VCA technology gain access to the rapid prototyping and production of mixed signal designs at a fraction of the cost of traditional full-custom development, yet with unit-pricing comparable to full-custom designs.

Creating Reusable Mixed-signal IP

Before IP can be reused, it must first be created. By comparing the VCA design process to the design process for a full-custom design, it becomes easy to see why VCA-based designs are easily reusable and why ease of design reuse is the essence of any viable mixed-signal IP concept. As shown in Figure 3, the ‘front-end’ portion of the VCA and full-custom design is identical. The first step is to split the design into analog and digital section. The digital portion of the design is captured as either an HDL or schematics, simulated, and synthesized into a gate-level netlist. The digital portion of the design is almost always captured as schematics and simulated with a SPICE-compatible simulator. Here is where the major divergence begins between the VCA and full-custom design flows.

Figure 3 - VCA flow facilitates soft IP reuse compared to full-custom’s hard IP output

Full-custom Layout

In a full-custom design, schematics and simulation are only rough models to guide the engineer in the “back-end” portion of the design. In the full-custom approach, the “back-end” portion of the design involves manually creating transistors and other circuit elements out of polygons in a layout editor. The “front-end” schematic database does not drive the layout process, instead the engineer acts as the manual synthesis, placement, and routing “tool” that creates every transistor and polygon in the design. Since all of the polygons and their interactions are new, the design must undergo physical extraction to determine the parasitics and couplings between adjacent and not-so-adjacent circuit structures. This parasitic/coupling analysis loop may require several iterations and is often a source of delay and increased expense in full-custom development efforts. Once the designer completes the “back-end” of the design, the output is a rectangular block of transistors with a rigid set of parameters that will be difficult to integrate or modify for future designs.

Via-configurable Arrays Enable Mixed-signal Soft IP

VCA architectures do not require full-custom layout because the mixed-signal resources are pre-placed along with a global routing fabric. The invention of analog-aware, via-only automatic place and route software allows the manual layout “back-end” to be replaced with an automated place and route “back-end.” Just as in digital design, where the HDL or schematic drives the synthesis and place and route process, the analog schematic and netlist in a VCA flow is the last manual step required to create a design or IP block. In the VCA flow, the digital gate-level netlist is merged with the analog SPICE-level netlist and this mixed signal netlist is the input to the via-only place and route software. As shown in Table 2, by capturing design intent at the schematic/netlist level, designers can create and reuse a wide range of mixed-signal IP blocks.

Table 2 - Reusable VCA mixed-signal soft IP

Designers can understand and integrate schematics and netlists much more readily than they can hard IP blocks. By providing designers with the ability to capture design intent in a “soft” format, VCA vendors will encourage the sharing and reuse of mixed-signal IP the same way that HDLs and synthesis enabled digital-only “soft-IP” reuse. Since VCA technology utilizes a single fabrication mask and requires no full-custom layout, the development time and cost, risk, and fabrication cost are reduced to the point that VCA development appears more like designing an FPGA than like the traditional full-custom endeavor. Like the FPGA companies, VCA providers are fabless semiconductor companies interested in selling silicon. As well as enabling customers to take advantage of with low development costs, VCA companies will encourage the use of their technology by providing low-cost development coupled with an ever-expanding and free mixed-signal IP library and with unit-pricing and performance on par with full-custom designs.