Archive for 2007

Arrow Electronics and Triad Semiconductor Team to Offer Mixed-Signal Via-Configurable Array ASICs

MELVILLE, N.Y. and WINSTON-SALEM, N.C. – Dec. 10, 2007 – The North American Components business of Arrow Electronics, Inc. (NYSE: ARW) and Triad Semiconductor, Inc., a leading mixed-signal ASIC provider, will make Triad’s mixed-signal via-configurable array ASICs available through Arrow’s North American sales and design centers. Arrow will provide technical sales and support and product [Read more...]

LVDS Transmitter and Receiver Drivers

Triad announces availability of its new LVDS Transmitter and Receiver drivers. These drivers can be used in such applications as; High Speed Backplane Driver, Complementary Clock Drivers, Level Translator, System Interconnects, ATM Applications, SDH Applications, High-Resolution Imaging Applications, Laser Printers, Digital Copiers, Stackable hubs for data communications, Digital Video, and High Definition Television. Both the [Read more...]

Soft IP for the Analog ASIC – Impossible Yet True

Via-configurable array (VCA) technology enables the rapid development and low cost design of feature-rich mixed-signal ASICs that integrate sophisticated analog IP blocks without the pain and risk of full-custom design. To IP or Not to IP Although all real engineers would like to create all of their designs from scratch, that just is not practical [Read more...]

Are Digital Structured ASICs Dead?

The Digital Structured ASIC is dead. LSI has pulled the plug. Synplicity is winding down their entire structured ASIC line. Articles appear, almost daily, waxing nostalgic about the rise and fall of an industry. Yet, there is a new approach to using a structured (or platform, or array) approach to ASIC design. Mixed signal via-configured [Read more...]

Via Configurable ASICs for Analog and Mixed Signal Applications

Introduction As any ASIC designer knows all to well, the pressure is relentless to develop larger chips with more functions (including analog) and to deliver in record time. Fabs keep making smaller geometry processes which allows for more transistors per unit area, but this does not make the design easier. And then there is the [Read more...]